SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
76 Reset, panic and debug events
WPC.CPU_DBRVEC
WPC.CPU_DBRVEC
0x104010
Field Bits Size Volatile? Synopsis Type
MMUOFF 0 1 — MMU (and hence cache) disable RW
Operation
When read
When written
HARD reset
Specifies whether the MMU is disabled when raising debug
events through DBRVEC.
Value - Description
0: Do not alter the state of SR.MMU.
1: Upon launch of the DBRVEC event handler for debug events,
the MMU will be forced to be disabled (that is, the MMU bit of
SR will be forced to 0).
Returns current value
Updates value
Undefined
— 1 1 — Reserved RES
Operation
When read
When written
HARD reset
Software should always write 0 to these bits. Software should
always ignore the value read from these bits.
Reads as 0 (behavior of other implementations may vary).
Writes ignored (behavior of other implementations may vary).
0 (behavior of other implementations may vary).
ADDRESS [2,31] 30 — DBRVEC address RW
Operation
When read
When written
Defines the address used for Reset, Panic and debug Events
when DBRVEC is selected.
Note that DEBUGRESET is always vectored through RESVEC.
D R A FT
Returns current value
Updates value
HARD reset
Undefined
Table 24: WPC.CPU_DBRVEC register definition
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0