SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
Key concepts 15
The SHdebug link provides:
• Full access to the physical address map (RAM, ROM, on-chip devices,
external-devices). This allows access to the debug registers (see Section
1.2.4: Debug registers on page 16).
• SH-5-originated access to a 16 Mbyte address space mapped over the SHdebug
link.
Allows a target debug agent (or any other code) to execute on the CPU without
requiring any external RAM or ROM, and thus enables use of SH-5 without a
traditional monitor ROM.
The debug/development tool must not access this 16 Mbyte region via the
SHdebug link (this would require the SH-5 reflect the request back to the tool).
The SH-5 behavior is undefined if this is attempted. The tool is expected to
service such memory accesses locally, without involving the SH-5.
• Control of the CPU via memory-mapped register.
Allows the CPU to be suspended, resumed, forced to execute from a specified
address, forced to generate a fast printf message, or forced to take a debug
interrupt.
• Streaming operations for CPU and bus trace information.
Allows trace information gathered from the CPU and the on-chip busses to be
copied to a specified area in the physical memory map (such as RAM or the
SHdebug link). This area acts as an external FIFO. The trace information can
also be sent directly to the SHdebug link using a special mode which compresses
the trace message contents. This gives better throughput on the link.
The SHdebug link is suitable for connection to a debug adaptor board as part of a
development tool (to provide code download and debug facilities). It can also be
connected to specialized hardware debug systems (such as logic analyzers) to
provide more complex facilities.
D R A FT
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug