SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
140 WP channel type IA
WPC.WP_IAx_MATCH_END
where x = channel ID
Field Bits Size Volatile? Synopsis Type
ADDRESS [31:0] 32 — End address RW
Operation
When read
When written
HARD reset
Defines the end address for the instruction address range.
When the MMU is enabled, this contains an effective address.
When the MMU is disabled, this contains a physical address.
The least significant bit (bit 0) should always be written as zero.
The effect of writing 1 to bit 0 is implementation-defined.
The address comparison is performed using the start address
of a SHmedia or SHcompact instruction (shown as Iaddr
below). The comparison is inclusive of the match start address,
but not of the match end address:
Iaddr >= start && Iaddr< end
Returns current value
Updates value
Undefined
— [63:32] 32 — Reserved RES
Operation
Reserved
When read Returns 0
When written
HARD reset 0
Ignored
Table 51: WPC.WP_IAx_MATCH_END register definition
D R A FT
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0