SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA 122 Debug protocols and interfaces // extract the least sig 7 bits result = (byteStream[0] & 127); // additionally, extract the most sig 7 bits result = result | ((byteStream[1] & 127)
PRELIMINARY DATA Debug protocols and interfaces 123 Common trace message fields Common trace message fields Field Size Header bit positions Description MESSAGE_TYPE 3-bits [2:0] Defines the basic contents of the debug message as described in Section : First word of message on page 118. Only field values of 0b010 (DTRC background trace message) and 0b011 (DTRC trigger trace message) relate to trace messages. SOURCE_MODULE 3-bits [5:3] Defines the on-chip source module which provides the information in the trace message a . Value - Description 0: WPC (CPU watchpoint controller) 1: SuperHyway bus analyzer 2-7 - Reserved for watchpoint logic in additional CPU cores or future accelerator modules. EVENT_TYPE 5-bits [10:6] Defines the watchpoint channel in the source module which generated the trace message. Refer to Table 4.1.6: Trace message header fields on page 247 for watchpoint channel numbers in the WPC and each of the bus analyzers. OVER_STALL 1-bit [11] This bit has two meanings depending on whether the stall-mode field of DM.TRCTL selects CPU stall mode or discard mode. See Table 31: DM.TRCTL definition on page 97. In stall mode, this bit is set when the CPU was stalled for some indeterminate time prior to this trace message being generated because there was no space available in the debug module FIFO. In discard mode, this bit is set to indicate that one or more watchpoint hits before this hit were discarded because there was no space available in the capture buffer. D R A FT Table 40: Common trace message fields 05-SA-10003 v1.0 SuperH, Inc. SH-5 System Architecture, Volume 3: Debug
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PRELIMINARY DATA SuperH TM (SH) 64-
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PRELIMINARY DATA Contents Preface 9
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PRELIMINARY DATA 5 1.8.11 DM.TRBUF
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PRELIMINARY DATA 7 3.2.5 Pin state
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PRELIMINARY DATA Preface This docum
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PRELIMINARY DATA Debug/trace archit
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PRELIMINARY DATA Overview of debug
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PRELIMINARY DATA Key concepts 15 Th
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PRELIMINARY DATA Key concepts 17 Ac
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PRELIMINARY DATA Key concepts 19 1.
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PRELIMINARY DATA Key concepts 21 1.
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PRELIMINARY DATA Key concepts 23 La
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PRELIMINARY DATA Key concepts 25 {W
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PRELIMINARY DATA Key concepts 27 If
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PRELIMINARY DATA Key concepts 29 Re
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PRELIMINARY DATA CPU control 31 1.3
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PRELIMINARY DATA CPU control 33 1.3
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PRELIMINARY DATA Watchpoint channel
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PRELIMINARY DATA Debug event action
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PRELIMINARY DATA WP channel matchin
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PRELIMINARY DATA WP channel matchin
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PRELIMINARY DATA WP channel type WP
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PRELIMINARY DATA SuperHyway bus ana
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PRELIMINARY DATA SuperHyway watchpo
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PRELIMINARY DATA Address comparison
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PRELIMINARY DATA Freezing bus maste
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PRELIMINARY DATA WP channel type PL
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PRELIMINARY DATA External debug int
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PRELIMINARY DATA SHdebug link 201 3
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PRELIMINARY DATA SHdebug link 205 T
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PRELIMINARY DATA SHdebug link 207 D
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PRELIMINARY DATA JTAG interface 213
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PRELIMINARY DATA Debug tool reset/s
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PRELIMINARY DATA Trigger functions
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PRELIMINARY DATA DBUS protocol 227
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PRELIMINARY DATA Implementation spe
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PRELIMINARY DATA Scalable parameter
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PRELIMINARY DATA Debug register add
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PRELIMINARY DATA Index A Actions 13
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PRELIMINARY DATA 267 244, . . . . .
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PRELIMINARY DATA 269 158-160, 166-1
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