SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
WP channel type WPC_PERF 173
WPC.WP_WPC_PERFx_MATCH_TYPE
where x = channel ID
Field Bits Size Volatile? Synopsis Type
PIPE_STALL 18 1 — Pipeline stall RW
TARGET_ADDRESS
_STALL
Operation
When read
When written
HARD reset
A pipeline stall occurred, due to a register or resource hazard
in the CPU or FPU.
Results in either 0 or N increments per instruction
(depending on number of stall cycles for that instruction’s
execution).
Returns current value
Updates value
Undefined
19 1 — Target address stall RW
Operation
When read
When written
HARD reset
A branch caused a pipeline stall (or NOP execution) due to
its target address not being available (that is, the prepare
target instruction (PTA, PTB, PTABS or PTREL) and branch
instruction were too close together).
Results in either 0 or N increments per instruction
(depending on number of stall cycles for that instruction’s
execution).
Returns current value
Updates value
Undefined
Table 60: WPC.WP_WPC_PERFx_MATCH_TYPE register definition
D R A FT
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug