SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
102 Debug module
DM.TRCTL
0x100040
Field Bits Size Volatile? Synopsis Type
STALL_MODE 8 1 — CPU stall mode RW
Operation
When read
When written
HARD reset 0
Defines the current CPU stall mode. This determines what happens
when the DM capture buffer fills.
Value - description
0: (Discard mode). Do not stall the CPU when the capture buffer
reaches its almost-full threshold. Instead, keep filling the capture
buffer with watchpoint hit entries from the WPC and when no space
is available, discard watchpoint hits which are unable to be written
into the capture buffer.
1: (Stall mode). Stall the CPU when the DM capture buffer reaches
its almost-full threshold. The CPU does not instantly react to a stall
request from the DM and by using an almost-full threshold, enough
space is available in the capture buffer for any additional watchpoint
hit entries which may occur.
Returns current value
Updates value
STALL_STATE 9 1 ✓ Current CPU stall/suspend state RO
Operation
When read
When written
Defines if the CPU is currently stalled due to the DM’s capture buffer
being almost-full or if the CPU is suspended.
Stall behavior is controlled by the stall_mode field.
Suspend behavior is controlled by the WPC.CPU_CTRL_ACTION
register (Section 1.3.1: Suspending/resuming the CPU on page 30).
Returns current value.
Value - Description
0: not stalled.
1: stalled
D R A FT
Ignored
HARD reset 0
Table 31: DM.TRCTL definition
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0