SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
Watchpoint channels 41
WPC.WP_nx_PRE
where
n = {IA/OA/IV/WPC_PERF},
x = channel ID
ISAMODE_
ENABLE
SR_MD_
ENABLE
Field Bits Size Volatile? Synopsis Type
[21:20] 2 — CPU ISA mode selection RW
Operation
When read
When written
HARD reset
Allows the CPU ISA mode to be included in the debug event
match.
For the IV WP channels, this field is still present, but its value is
ignored in the pre-condition checking. IV channels never match
in SHcompact mode.
Value - Description
0b00, 0b11: match irrespective of the current CPU ISA mode.
0b01: only match if CPU is executing SHmedia instructions.
0b10: only match if CPU is executing SHcompact instructions.
Returns current value
Updates value
Undefined
[23:22] 2 — CPU user/privileged mode selection RW
Operation
When read
When written
HARD reset
Allows the CPU user/privileged mode to be included in the
debug event match.
Value - Description
0b00, 0b11: match irrespective of the current CPU user/
privileged mode.
0b01: only match if CPU is in user mode.
0b10: only match if CPU is in privileged mode.
D R A FT
Returns current value
Updates value
Undefined
Table 14: WPC.WP_{IA/OA/IV/WPC_PERF}x_PRE register definition
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug