SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

More documents

Recommendations

Info

PRELIMINARY DATA 254 Debug register address map DM module-specific control registers 17 registers currently assigned Module-specific address group DM.ECOUNT_VALUE0 DM.PCOUNT_VALUE0 DM.PCOUNT_VALUE1 Counter address group Six DM.WP_PL0_Regs 10-words per channel spare Six DM.WP_PL1_Regs Bus analyzer address group Figure 18: DM control register groups DM.WP_IA0_PRE DM.WP_IA0_ACTION 6-words per channel spare DM.WP_IA1_PRE DM.WP_IA1_ACTION DM.WP_PL1_PRE DM.WP_PL1_ACTION Watchpoint channels address group 10 watchpoint channels currently assigned D R A FT SuperH, Inc. SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0
PRELIMINARY DATA Debug register address map 255 4.2.3 Complete register list Note: The offsets given below are relative to either the CPU base address, or the DM base address, according to whether the register name prefix is “WPC” or “DM”. See the SH-5 System Architecture Manual for the address map. All registers shown in this table must be accessed using 64-bit operations. When writing to the registers from the instruction stream, suitable instructions are listed in Table 1: Instructions for accessing WPC and DM registers on page 17. WPC chain latches Register name Offset References WPC.IA_CHAIN_0 WPC.IA_CHAIN_1 0x100000 0x100008 Section 1.2.8: Chain latches on page 21 and Table 6: WPC.IA_CHAIN_x WPC.IA_CHAIN_2 0x100010 definition on page 26 WPC.IA_CHAIN_3 WPC.CHAIN_0 WPC event counters 0x100018 0x100020 WPC.ECOUNT_VALUE_0 0x200000 Section 1.2.8: Chain latches on page 21. WPC performance counters WPC CPU control WPC.PCOUNT_VALUE_0 0x204000 Section 1.2.10: Performance counters on page 28 and WPC.PCOUNT_VALUE_1 0x204008 Table 8 on page 29. D R A FT WPC.CPU_CTRL_ACTION 0x104000 Section 1.3: CPU control on page 30. WPC.CPU_DBRMODE 0x104008 WPC.CPU_DBRMODE on page 74. WPC.CPU_DBRVEC 0x104010 WPC.CPU_DBRVEC on page 76 Table 94: Register map and references 05-SA-10003 v1.0 SuperH, Inc. SH-5 System Architecture, Volume 3: Debug
Page 1 and 2:
PRELIMINARY DATA SuperH TM (SH) 64-
Page 3 and 4:
PRELIMINARY DATA Contents Preface 9
Page 5 and 6:
PRELIMINARY DATA 5 1.8.11 DM.TRBUF
Page 7 and 8:
PRELIMINARY DATA 7 3.2.5 Pin state
Page 9 and 10:
PRELIMINARY DATA Preface This docum
Page 11 and 12:
PRELIMINARY DATA Debug/trace archit
Page 13 and 14:
PRELIMINARY DATA Overview of debug
Page 15 and 16:
PRELIMINARY DATA Key concepts 15 Th
Page 17 and 18:
PRELIMINARY DATA Key concepts 17 Ac
Page 19 and 20:
PRELIMINARY DATA Key concepts 19 1.
Page 21 and 22:
PRELIMINARY DATA Key concepts 21 1.
Page 23 and 24:
PRELIMINARY DATA Key concepts 23 La
Page 25 and 26:
PRELIMINARY DATA Key concepts 25 {W
Page 27 and 28:
PRELIMINARY DATA Key concepts 27 If
Page 29 and 30:
PRELIMINARY DATA Key concepts 29 Re
Page 31 and 32:
PRELIMINARY DATA CPU control 31 1.3
Page 33 and 34:
PRELIMINARY DATA CPU control 33 1.3
Page 35 and 36:
PRELIMINARY DATA Watchpoint channel
Page 37 and 38:
Page 39 and 40:
Page 41 and 42:
Page 43 and 44:
Page 45 and 46:
Page 47 and 48:
Page 49 and 50:
PRELIMINARY DATA Debug event action
Page 51 and 52:
Page 53 and 54:
Page 55 and 56:
Page 57 and 58:
Page 59 and 60:
Page 61 and 62:
Page 63 and 64:
Page 65 and 66:
Page 67 and 68:
PRELIMINARY DATA WP channel matchin
Page 69 and 70:
Page 71 and 72:
Page 73 and 74:
PRELIMINARY DATA Reset, panic and d
Page 75 and 76:
Page 77 and 78:
Page 79 and 80:
Page 81 and 82:
Page 83 and 84:
Page 85 and 86:
PRELIMINARY DATA Debug module 85 DM
Page 87 and 88:
PRELIMINARY DATA Debug module 87
Page 89 and 90:
PRELIMINARY DATA Debug module 89 Wh
Page 91 and 92:
PRELIMINARY DATA Debug module 91 St
Page 93 and 94:
PRELIMINARY DATA Debug module 93 Mu
Page 95 and 96:
PRELIMINARY DATA Debug module 95 1.
Page 97 and 98:
PRELIMINARY DATA Debug module 97 1.
Page 99 and 100:
PRELIMINARY DATA Debug module 99 DM
Page 101 and 102:
PRELIMINARY DATA Debug module 101 D
Page 103 and 104:
Page 105 and 106:
Page 107 and 108:
PRELIMINARY DATA Debug module 107 1
Page 109 and 110:
Page 111 and 112:
Page 113 and 114:
PRELIMINARY DATA Debug module 113
Page 115 and 116:
Page 117 and 118:
PRELIMINARY DATA Debug module 117 1
Page 119 and 120:
PRELIMINARY DATA Debug protocols an
Page 121 and 122:
Page 123 and 124:
Page 125 and 126:
Page 127 and 128:
Page 129 and 130:
Page 131 and 132:
Page 133 and 134:
Page 135 and 136:
Page 137 and 138:
PRELIMINARY DATA WP channel type BR
Page 139 and 140:
PRELIMINARY DATA WP channel type IA
Page 141 and 142:
PRELIMINARY DATA WP channel type IA
Page 143 and 144:
PRELIMINARY DATA WP channel type OA
Page 145 and 146:
Page 147 and 148:
Page 149 and 150:
Page 151 and 152:
Page 153 and 154:
PRELIMINARY DATA WP channel type IV
Page 155 and 156:
PRELIMINARY DATA WP channel type IV
Page 157 and 158:
Page 159 and 160:
Page 161 and 162:
Page 163 and 164:
PRELIMINARY DATA WP channel type FP
Page 165 and 166:
PRELIMINARY DATA WP channel type WP
Page 167 and 168:
Page 169 and 170:
Page 171 and 172:
Page 173 and 174:
Page 175 and 176:
Page 177 and 178:
Page 179 and 180:
PRELIMINARY DATA SuperHyway bus ana
Page 181 and 182:
PRELIMINARY DATA SuperHyway watchpo
Page 183 and 184:
PRELIMINARY DATA Address comparison
Page 185 and 186:
PRELIMINARY DATA Freezing bus maste
Page 187 and 188:
PRELIMINARY DATA WP channel type PL
Page 189 and 190:
Page 191 and 192:
Page 193 and 194:
Page 195 and 196:
Page 197 and 198:
Page 199 and 200:
PRELIMINARY DATA External debug int
Page 201 and 202:
PRELIMINARY DATA SHdebug link 201 3
Page 203 and 204: PRELIMINARY DATA SHdebug link 203 3
Page 205 and 206: PRELIMINARY DATA SHdebug link 205 T
Page 207 and 208: PRELIMINARY DATA SHdebug link 207 D
Page 213 and 214: PRELIMINARY DATA JTAG interface 213
Page 219 and 220: PRELIMINARY DATA Debug tool reset/s
Page 225 and 226: PRELIMINARY DATA Trigger functions
Page 227 and 228: PRELIMINARY DATA DBUS protocol 227
Page 241 and 242: PRELIMINARY DATA Implementation spe
Page 243 and 244: PRELIMINARY DATA Scalable parameter
Page 253: PRELIMINARY DATA Debug register add
Page 257 and 258: PRELIMINARY DATA Debug register add
Page 265 and 266: PRELIMINARY DATA Index A Actions 13
Page 267 and 268: PRELIMINARY DATA 267 244, . . . . .
Page 269 and 270: PRELIMINARY DATA 269 158-160, 166-1
show all

SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?