SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
Reset, panic and debug events 83
State of DM.EXP_CAUSE bits
Value
read
Meaning
Value
written
Effect
1 Interrupt source was
asserted
0 The interrupt source will be de-asserted.
Note that some interrupt sources require
additional actions to fully de-assert them (see
Table 29 on page 83).
1 Writing 1 has no effect on the bit’s value.
Table 28: State of reading/writing DM.EXP_CAUSE bits
The DEBUGINT handler should write ‘0’ to the appropriate bit(s) in DM.EXP_CAUSE as
soon as it can. This will minimize the risk of losing new interrupts that arrive
during the execution of the DEBUGINT handler.
DM.EXP_CAUSE
0x100010
Field Bits Size Volatile? Synopsis Type
DM_FIFO_INTERRUPT 0 1 ✓ DM FIFO interrupt RW
Operation
When read
When written
HARD reset 0
This field is set whenever an interrupt is generated due to
DM FIFO activity as selected by the FF_THRESH field of
DM.TRCTL (see Table 31 on page 97).
Returns current value
Updates value.
Writing 0 Will partially clear the cause of the DM FIFO
interrupt. In order to fully clear the interrupt, the DM FIFO
must be setup to remove the cause (either reprogram
DM.TRCTL.FF_THRESH such that it will not generate debug
Interrupts or empty the DM FIFO).
Writing 1 has no effect - any pending DM FIFO interrupts will
not be lost, and subsequent reads will return 1 (unless the
source of the interrupt is unexpectedly removed).
D R A FT
Table 29: DM.EXP_CAUSE register definition
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug