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SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA<br />

Watchpoint channels 45<br />

DM.WP_PLx_PRE<br />

where x = channel ID<br />

Field Bits Size Volatile? Synopsis Type<br />

ECOUNT_ENABLE 7 1 — Event counter enable RW<br />

Operation See the ECOUNT_ENABLE field of Table 14 on page 38.<br />

When read<br />

When written<br />

HARD reset<br />

DM.WP_FPF_PRE:<br />

Returns current value<br />

Updates value<br />

Undefined<br />

ECOUNT_ID [11:8] 4 — Event counter ID RW<br />

Operation See the ECOUNT_ID field of Table 14 on page 38<br />

When read<br />

When written<br />

HARD reset<br />

Returns current value<br />

Updates value<br />

Undefined<br />

— [63:12] 52 — Reserved RES<br />

Operation<br />

Reserved<br />

When read Return 0<br />

When written<br />

HARD reset 0<br />

Ignored<br />

Table 16: DM.WP_PLx_PRE register definition<br />

The fast printf function has an associated PRE register.<br />

D R A FT<br />

05-SA-10003 v1.0<br />

<strong>SuperH</strong>, Inc.<br />

<strong>SH</strong>-5 <strong>System</strong> <strong>Architecture</strong>, <strong>Volume</strong> 3: Debug

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