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SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA<br />

WP channel type BR 159<br />

DM.WP_BR_FILTER<br />

0x100028<br />

Field Bits Size Volatile? Synopsis Type<br />

RTE 19 1 — RTE branch trace enable RW<br />

Operation<br />

When read<br />

When written<br />

HARD reset<br />

Match for RTE instruction executions (apart from those which<br />

restore SR.WATCH to ‘1’, see Section 1.6.1: SR.WATCH <strong>bit</strong> on<br />

page 66).<br />

See Section 1.14.3: Precondition checking for events and RTE<br />

on page 161 regarding precondition checks for SR_MD_ENABLE<br />

when tracing RTE.<br />

Returns current value<br />

Updates value<br />

Undefined<br />

EVENT 20 1 — Event branch trace enable RW<br />

ENABLE_TRACE<br />

_TIMESTAMP<br />

ACTION_TRIG_<br />

OUT<br />

Operation<br />

When read<br />

When written<br />

HARD reset<br />

Match for all interrupts and all exceptions.<br />

See Section 1.14.3: Precondition checking for events and RTE<br />

on page 161 regarding precondition checks for SR_MD_ENABLE<br />

when tracing events.<br />

Returns current value<br />

Updates value<br />

Undefined<br />

21 1 — Enable trace timestamp RW<br />

See the ENABLE_TRACE_TIMESTAMP field of Table 19 on page 54<br />

22 1 — Trigger out enable RW<br />

D R A FT<br />

See the ACTION_TRIG_OUT field of Table 19 on page 54<br />

Table 58: DM.WP_BR_FILTER register definition<br />

05-SA-10003 v1.0<br />

<strong>SuperH</strong>, Inc.<br />

<strong>SH</strong>-5 <strong>System</strong> <strong>Architecture</strong>, <strong>Volume</strong> 3: Debug

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