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SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA<br />

WP channel type BR 161<br />

1.14.3 Precondition checking for events and RTE<br />

When an event is traced, the DM.WP_BRX_FILTER.SR_MD_ENABLE field is checked<br />

against the CPU mode (SR.MD) of the interrupted or excepting instruction.<br />

This allows the branch channel to filter between interrupts/exceptions occurring in<br />

user mode and those occurring in privileged mode.<br />

When an RTE is traced, the DM.WP_BRX_FILTER.SR_MD_ENABLE field is checked<br />

against the CPU mode (SR.MD) of the first instruction executed after the RTE.<br />

This allows the branch channel to filter between RTEs which return to user mode<br />

and those which return to privileged mode.<br />

An RTE instruction may return to a user-mode instruction which itself excepts and<br />

causes a new exception handler to be launched. In this case, it is<br />

implementation-defined whether the user-mode instruction is treated as having run<br />

in user mode or privileged mode. The DM.WP_BRX_FILTER.SR_MD_MODE <strong>bit</strong>s might<br />

not work as expected in this situation.<br />

1.14.4 Source and destination addresses in branch trace<br />

messages<br />

Table 59 defines the selection of source and destination addresses for branch trace<br />

messages in a number of situations. The branch source address is always the<br />

address of the most recent completed instruction occurring before the jump in PC<br />

value. In particular, this means an excepting instruction’s PC can never be shown as<br />

the source of a branch.<br />

Scenario No. a Source<br />

Destination<br />

(See footnote c )<br />

D R A FT<br />

Branch<br />

type b<br />

<strong>SH</strong>media branch at PC=X, target PC=Y X Y Branch<br />

<strong>SH</strong>compact non-delayed branch at PC=X, target PC=Y X Y Branch<br />

<strong>SH</strong>compact delayed branch at PC=X, target PC=Y X+2 Y Branch<br />

RTE at PC=X, new PC=Y, Y does not except X Y RTE<br />

Table 59: Selection of branch source and destination addresses<br />

05-SA-10003 v1.0<br />

<strong>SuperH</strong>, Inc.<br />

<strong>SH</strong>-5 <strong>System</strong> <strong>Architecture</strong>, <strong>Volume</strong> 3: Debug

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