SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
Debug module 91
Stall/discard overview
The DM.TRCTL register (see Section 1.8.10: DM.TRCTL (trace/trigger register) on
page 97) has a field (DM.TRCTL.STALL_MODE) which determines the action if there is
no space available in the capture buffer at the time a WPC watchpoint hit or BR
watchpoint hit occurs. The two possible actions are:
• stall the CPU until space becomes available in the capture buffer or
• discard watchpoint hits which are unable to be written to the capture buffer.
All actions (other than controlling the non-BR hit trigger-out signal) are performed
at the output of the capture buffer. This means that in stall mode (see
Table 31: DM.TRCTL definition on page 97), actions will be delayed when the
capture buffer fills and the processor stalls. In discard mode, when the capture
buffer fills, the following occur until space becomes available:
• subsequent watchpoint hits will be discarded,
When space does become available in the capture buffer, the next trace message
generated due to a WP hit will have its overstall bit set to 1 to denote that WP
hits have been lost.
• DM ACTION_CHAIN_ALTER actions for IA/IV/OA/BR hits are voided,
• ACTION_TRIG_OUT actions for BR hits are voided,
• ACTION_TRACE actions for IA/IV/OA/BR hits are voided.
(WPC ACTION_CHAIN_ALTER actions for IA/IV/OA hits are performed normally in
this situation and are not voided.)
Generation of trigger-out pulses for IA/IV/OA hits is performed at the input to the
capture buffer, and thus is performed even in discard mode. However, the length of
the trigger-out pulse can cover several distinct WP hits occurring.
Stall mode
D R A FT
The CPU pipeline cannot be instantly stalled. When a stall signal from the DM is
asserted, the pipeline stops fetching new instructions which causes the pipeline to
empty an implementation defined number of clock cycles later (see DM FIFO
high-water mark on page 246). Only at this time is the CPU stalled and unable to
generate any more watchpoint hits.
The determination of the size of the capture buffer must allow for this CPU stall
latency. The capture buffer includes “high-water” detection logic which asserts the
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SH-5 System Architecture, Volume 3: Debug