SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
82 Reset, panic and debug events
The CPU will launch a DEBUGINT when these 3 conditions are met:
Value
read
• SR.BL = 0
• At least one bit of DM.EXP_CAUSE is set. If SR.BL=1 when a cause bit is first
asserted, at least one cause bit must still be asserted when SR.BL changes to 0.
• In at least one clock cycle since the last DEBUGINT launch or reset (of any kind),
all bits of DM.EXP_CAUSE have been clear.
If a bit in DM.EXP_CAUSE is set then subsequently cleared, with SR.BL=1 all the time,
no DEBUGINT will occur.
If the handler for DEBUGINT deals with some conditions signalled in DM.EXP_CAUSE
but leaves others asserted, there will not be another DEBUGINT after the handler
returns. A handler for DEBUGINT must be written to handle all asserted conditions,
clear the handled conditions in DM.EXP_CAUSE (see below) and ensure that
DM.EXP_CAUSE has been read back with all bits clear before returning. This ensures
a new DEBUGINT can occur when a cause is next asserted.
The write semantics of DM.EXP_CAUSE are such that a handler can clear the cause
bits selectively.
Each bit of DM.EXP_CAUSE corresponds to a source of DEBUGINT, Table 28 shows the
state indicated when reading these bits, and the effect of writing them. Table 29
shows which bits in the register correspond to specific interrupt sources.
Meaning
0 Interrupt source was not
asserted
State of DM.EXP_CAUSE bits
Value
written
Effect
0 The interrupt source will remain not asserted.
If the interrupt source has been asserted since
the register was read, this will actually clear the
interrupt without its condition being properly
handled. For this reason, writing 0 to a bit which
was read as 0 is not advised.
D R A FT
1 Writing 1 has no effect on the bit’s value.
Table 28: State of reading/writing DM.EXP_CAUSE bits
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0