SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
WP channel type FPF 163
1.15 WP channel type FPF
Triggers whenever DM.FPF register is written. The trigger occurs immediately after
the execution of the memory write instruction which caused it.
The FPF channel is unaffected by SR.WATCH.
1.15.1 Match registers
There are no associated match or action registers. Certain fields in the generic
DM.WP_FPF_PRE register define the pre-conditions.
1.15.2 Event specifics
Note:
Source CPU
Reason: The DM.FPF register was written to.
Undefined behavior
Writing to the DM.WP_FPF_PRE register when the WP channel is enabled.
As explained in Access to registers on page 17, instructions which write to WPC/DM
memory mapped registers should be followed by a SYNCO instruction. In the case of
writing to DM.FPF, omitting the SYNCO instruction may result in the FPF message
having an incorrect PC value.
Fields in DM.WP_FPF_PRE:
BASIC_ENABLE, ASID_ENABLE, ASID_VALUE, CHAIN_ENABLE, CHAIN_ID - Supported
ECOUNT_ENABLE, ECOUNT_ID Not supported
WPC.WP_FPFX_PRE does not exist
WPC.WP_FPFX_ACTION does not exist
DM.WP_FPFX_ACTION does not exist:
D R A FT
The action is implicit, a trigger trace message is generated (see Figure 45: FPF
Watchpoint Trace Message on page 130):
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug