SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
162 WP channel type BR
Scenario No. a Source
Destination
(See footnote c )
Branch
type b
RTE at PC=X, new PC=Y, Y excepts, handler at PC=Z 1 X Y RTE
SHmedia PC=X excepts, handler at PC=Z (X is not the target
of a taken branch)
SHcompact PC=X excepts, handler at PC=Z (X is not the
target of a taken branch)
SHmedia branch at PC=X, target at PC=Y excepts, handler
at PC=Z
SHcompact delayed branch at PC=X, delay slot at
PC=X+2, target at PC=Y excepts, handler at PC=Z
SHcompact branch (delayed or non-delayed) at PC=X
excepts, handler at PC=Z
SHcompact delayed branch at PC=X, delay slot at X+2
excepts, handler at PC=Z
RTE at PC=X, new PC=Y is a SHcompact branch which
excepts, handler at PC=Z
RTE at PC=X, new PC=Y is a SHcompact delayed branch
whose delay slot excepts, handler at PC=Z
2 X Z Event
X-4 Z Event
X-2 Z Event
1 X Y Branch
2 X Z Event
1 X+2 Y Branch
2 X+2 Z Event
X-2 Z Event
X Z Event
1 X Y RTE
2 X Z Event
1 X Y RTE
2 Y Z Event
Table 59: Selection of branch source and destination addresses
a. Some scenarios generate more than one BR channel trigger. When this happens, the
triggers are numbered in the order they occur.
D R A FT
b. Where branch is shown in this column, it means either unconditional or conditional,
depending on the branch type.
c. For addresses of instructions in SHmedia mode, the value in the trace packet has the
least significant bit set. For addresses of instructions in SHcompact mode, the value in
the trace packet has the least significant bit clear.
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0