SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
78 Reset, panic and debug events
The debug event sequence is identical for both of these circumstances, but there are
differences in the data available to the exception handler according to the WP
channel type. This state is described in the WP channel type sections of this
document (Section 1.10 through Section 1.18).
In a given processor cycle, multiple debug events can match, each of which can
potentially have its action set to raise a debug exception. In these circumstances, a
single debug event (the highest priority debug exception which matches) will be
raised. These priorities are defined in Section 1.7.3: Event specific information on
page 80. There are two general approaches that can be used to cope with
instructions that hit more than one excepting condition:
1 The debug event handler could work out which other conditions would have hit
and carry out all the actions.
2 The debug handler can temporarily disable the exception action from the
channel(s) which hit and caused the exception. When the excepting instruction is
restarted by the RTE at the end of the handler, lower priority exceptions will get
a chance to launch. The handler should enable single stepping, so that a
DEBUGSS exception will be taken on completion of the instruction. The DEBUGSS
handler can re-instate any channels’ ACTION_EXCEPTION actions that were
temporarily disabled.
MMU disable
Either RESVEC or DBRVEC is used to vector debug events (see Section 1.7.1).
Both RESVEC and DBRVEC provide a MMUOFF field to allow the MMU to be disabled
when launching the event handler due to debug events (when launching for
non-debug events such as reset or panic, the MMU is always disabled).
Disabling the MMU allows the debug event handler to execute without having to
reserve TLB entries in the application being debugged. Thus it is possible to totally
decouple the debug event handler from the debugger. It also allows execution of code
with the caches disabled, thus it is possible to perform debug event handling
without perturbing the caches.
D R A FT
If the MMUOFF bit of RESVEC/DBRVEC is set, the MMU will be forced to be disabled
whenever the debug event handler is launched (that is, the MMU bit of SR will be
forced to 0).
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0