SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA 230 DBUS protocol 3.6.6 Endian-specific behavior Data size The msk field determines which bytes in the data field are significant. The manner in which the bytes within the data field correspond to offsets from the address field is dependant on the endianness of the target system. This is illustrated in Table 81. Mask Byte positions within 8-byte data field D R A FT Address offset in endian mode: 7 6 5 4 3 2 1 0 Big Little 8 0xFF MSB LSB 0 0 4 0x0F MSB LSB 4 0 4 0xF0 MSB LSB 0 4 2 0x03 MSB LSB 6 0 2 0x0C MSB LSB 4 2 2 0x30 MSB LSB 2 4 2 0xC0 MSB LSB 0 6 1 0x1 7 0 1 0x2 6 1 1 0x4 5 2 1 0x8 4 3 1 0x10 3 4 1 0x20 2 5 1 0x40 1 6 1 0x80 0 7 Table 81: DBUS mask/address mapping for big and little endian modes SuperH, Inc. SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0
PRELIMINARY DATA DBUS protocol 231 3.6.7 Opcode definition Opcode type Binary Value Hexadecimal Name Reference Requests 0b00110001 0x31 Load8 Load8 on page 232. 0b01000001 0x41 Load16 Load16 on page 233. 0b01010001 0x51 Load32 Load32 on page 234 0b00110010 0x32 Store8 Store8 on page 235 0b01000010 0x42 Store16 Store16 on page 236 0b01010010 0x52 Store32 Store32 on page 237 0b00110101 0x35 Swap8 Swap8 - swap 8 bytes on page 238 0b00011000 0x18 Flush Flush - flush a physical address on page 239 0b00001000 0x8 Purge Purge - purge a physical address on page 240 Responses 0b10000000 0x80 Success 0b10000001 0x81 Failure Table 82: DBUS opcode values D R A FT 05-SA-10003 v1.0 SuperH, Inc. SH-5 System Architecture, Volume 3: Debug
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PRELIMINARY DATA SuperH TM (SH) 64-
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PRELIMINARY DATA Contents Preface 9
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PRELIMINARY DATA 5 1.8.11 DM.TRBUF
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PRELIMINARY DATA 7 3.2.5 Pin state
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PRELIMINARY DATA Preface This docum
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PRELIMINARY DATA Debug/trace archit
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PRELIMINARY DATA Overview of debug
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PRELIMINARY DATA Key concepts 15 Th
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PRELIMINARY DATA Key concepts 17 Ac
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PRELIMINARY DATA Key concepts 19 1.
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PRELIMINARY DATA Key concepts 21 1.
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PRELIMINARY DATA Key concepts 23 La
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PRELIMINARY DATA Key concepts 25 {W
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PRELIMINARY DATA Key concepts 27 If
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PRELIMINARY DATA Key concepts 29 Re
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PRELIMINARY DATA CPU control 31 1.3
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PRELIMINARY DATA CPU control 33 1.3
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PRELIMINARY DATA Watchpoint channel
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PRELIMINARY DATA Debug event action
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PRELIMINARY DATA WP channel matchin
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PRELIMINARY DATA Reset, panic and d
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PRELIMINARY DATA Debug module 85 DM
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PRELIMINARY DATA Debug module 87
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PRELIMINARY DATA Debug module 89 Wh
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PRELIMINARY DATA Debug module 91 St
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PRELIMINARY DATA Debug module 93 Mu
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PRELIMINARY DATA Debug module 95 1.
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PRELIMINARY DATA Debug module 97 1.
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PRELIMINARY DATA Debug module 99 DM
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PRELIMINARY DATA Debug module 101 D
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PRELIMINARY DATA Debug module 107 1
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PRELIMINARY DATA Debug module 113
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PRELIMINARY DATA Debug module 117 1
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PRELIMINARY DATA Debug protocols an
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PRELIMINARY DATA WP channel type BR
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PRELIMINARY DATA WP channel type IA
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PRELIMINARY DATA WP channel type IA
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PRELIMINARY DATA WP channel type OA
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PRELIMINARY DATA WP channel type IV
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PRELIMINARY DATA WP channel type IV
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PRELIMINARY DATA WP channel type FP
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PRELIMINARY DATA WP channel type WP
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Page 179 and 180: PRELIMINARY DATA SuperHyway bus ana
Page 181 and 182: PRELIMINARY DATA SuperHyway watchpo
Page 183 and 184: PRELIMINARY DATA Address comparison
Page 185 and 186: PRELIMINARY DATA Freezing bus maste
Page 187 and 188: PRELIMINARY DATA WP channel type PL
Page 199 and 200: PRELIMINARY DATA External debug int
Page 201 and 202: PRELIMINARY DATA SHdebug link 201 3
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Page 207 and 208: PRELIMINARY DATA SHdebug link 207 D
Page 213 and 214: PRELIMINARY DATA JTAG interface 213
Page 219 and 220: PRELIMINARY DATA Debug tool reset/s
Page 225 and 226: PRELIMINARY DATA Trigger functions
Page 227 and 228: PRELIMINARY DATA DBUS protocol 227
Page 229: PRELIMINARY DATA DBUS protocol 229
Page 241 and 242: PRELIMINARY DATA Implementation spe
Page 243 and 244: PRELIMINARY DATA Scalable parameter
Page 253 and 254: PRELIMINARY DATA Debug register add
Page 265 and 266: PRELIMINARY DATA Index A Actions 13
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Page 269 and 270: PRELIMINARY DATA 269 158-160, 166-1
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