SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
7
3.2.5 Pin state during reset 203
3.2.6 Start of message indication 204
3.2.7 Flow control 204
3.2.8 SHdebug link output protocol 205
3.2.9 SHdebug link input protocol 208
3.2.10 Debug-link message examples 209
3.2.1 SHdebug link control registers 211
3.3 JTAG interface 212
3.3.1 Introduction 212
3.3.2 Basic concepts 212
3.3.3 Debug interface selection 213
3.3.4 JTAG debug message protocol 213
3.4 Debug tool reset/suspend behavior 219
3.4.1 DEBUG reset 219
3.4.2 Reset functions available from debug tools 219
3.4.3 CPU suspend function 223
3.5 Trigger functions 225
3.6 DBUS protocol 226
3.6.1 Overview 226
3.6.2 Nibble order 228
3.6.3 Pipelining of DBUS requests 228
3.6.4 Unsolicited responses 229
3.6.5 Critical word ordering 229
3.6.6 Endian-specific behavior 230
3.6.7 Opcode definition 231
D R A FT
3.6.8 DBUS transactions 232
4 Implementation specifics 241
4.1 Scalable parameters 241
4.1.1 WP channels 241
4.1.2 Event counters 242
4.1.3 Performance counters 243
4.1.4 Chain latches 243
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug