SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
CPU control 31
1.3.2 Control operations
The control operation is defined by a 2-bit value:
Operation name value Explanation
CPU_CTRL_OP_SUSPEND 0b00 Suspends execution of the receiving CPU. See
Section 1.3.1: Suspending/resuming the CPU on
page 30.
CPU_CTRL_OP_RESUME 0b01 Resumes execution from suspended state of the
receiving CPU
CPU_CTRL_OP_CPURESET 0b10 Generate a CPURESET event on the receiving CPU.
See Section 1.7: Reset, panic and debug events on
page 73.
CPU_CTRL_OP_DEBUGRESET 0b11 Generate a DEBUGRESET event for the whole
device.
See Section 1.7: Reset, panic and debug events on
page 73.
WPC.CPU_CTRL_ACTION register definition
When written to, this register performs a CPU control operation:
WPC.CPU_CTRL_ACTION
Table 9: CPU control operation values
0x104000
Field Bits Size Volatile? Synopsis Type
OPCODE [1:0] 2 — Control operation code RW
D R A FT
Operation A CPU control operation as defined in Table 9 on page 31.
When read
Returns current value
When written Performs the operation defined in Table 9 on page 31.
HARD reset
Undefined
Table 10: WPC.CPU_CTRL_ACTION register definition
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug