SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA 240 DBUS protocol Purge - purge a physical address Forces any data held by a module and associated with a physical address to be made coherent with the actual data held at the physical address whilst removing any copies of the data held in the target module. Request OPC[7:0] ADDR[31:0] SRC[7:0] TID[7:0] DUMMY[7:0] DATA[63:0] Response R_OPC[7:0] R_SRC[7:0] R_TID[7:0] Opcode Purge (0x8). Address, where ADDR[31:24] identifies the module. ADDR[23:3] specifies the offset within the module. ADDR[2:0] is not significant. Source identifier, defined by the system not the module. Transaction identifier, defined by the module not the system. Dummy bits. Address to be purged. Response type, either 0x80 for Success, or 0x81 for Failure. Copy of SRC. Copy of TID. D R A FT SuperH, Inc. SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0
PRELIMINARY DATA Implementation specifics 4.1 Scalable parameters The number of various debug facilities is scalable. This section defines these specifics for the SH-5 evaluation device. 4.1.1 WP channels SH-5 evaluation device provides the following channels: Base channel name Locality Function Number of channels BRK WPC CPU 1 BRK0 D R A FT 4 Actual channel names IA WPC Instruction address 4 IA0 thru IA3 OA WPC Operand address 2 OA0 thru OA1 IV WPC Instruction value 2 IV0 thru IV1 BR DM Branch trace 1 BR0 FPF DM Fast printf 1 FPF0 PL DM SuperHyway bus analyzer 2 PL0 thru PL1 DM DM Debug module 1 DM0 WPC_PERF WPC CPU performance monitor 2 WPC_PERF0 thru WPC_PERF1 Table 83: SH-5 evaluation device WP channels 05-SA-10003 v1.0 SH-5 System Architecture, Volume 3: Debug
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PRELIMINARY DATA SuperH TM (SH) 64-
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PRELIMINARY DATA Contents Preface 9
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PRELIMINARY DATA 5 1.8.11 DM.TRBUF
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PRELIMINARY DATA 7 3.2.5 Pin state
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PRELIMINARY DATA Preface This docum
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PRELIMINARY DATA Debug/trace archit
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PRELIMINARY DATA Overview of debug
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PRELIMINARY DATA Key concepts 15 Th
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PRELIMINARY DATA Key concepts 17 Ac
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PRELIMINARY DATA Key concepts 19 1.
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PRELIMINARY DATA Key concepts 21 1.
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PRELIMINARY DATA Key concepts 23 La
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PRELIMINARY DATA Key concepts 25 {W
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PRELIMINARY DATA Key concepts 27 If
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PRELIMINARY DATA Key concepts 29 Re
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PRELIMINARY DATA CPU control 31 1.3
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PRELIMINARY DATA CPU control 33 1.3
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PRELIMINARY DATA Watchpoint channel
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PRELIMINARY DATA Debug event action
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PRELIMINARY DATA WP channel matchin
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PRELIMINARY DATA Reset, panic and d
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PRELIMINARY DATA Debug module 85 DM
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PRELIMINARY DATA Debug module 87
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PRELIMINARY DATA Debug module 89 Wh
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PRELIMINARY DATA Debug module 91 St
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PRELIMINARY DATA Debug module 93 Mu
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PRELIMINARY DATA Debug module 95 1.
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PRELIMINARY DATA Debug module 97 1.
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PRELIMINARY DATA Debug module 99 DM
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PRELIMINARY DATA Debug module 101 D
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PRELIMINARY DATA Debug module 107 1
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PRELIMINARY DATA Debug module 113
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PRELIMINARY DATA Debug module 117 1
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PRELIMINARY DATA Debug protocols an
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PRELIMINARY DATA WP channel type BR
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PRELIMINARY DATA WP channel type IA
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PRELIMINARY DATA WP channel type IA
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PRELIMINARY DATA WP channel type OA
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PRELIMINARY DATA WP channel type IV
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PRELIMINARY DATA WP channel type IV
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PRELIMINARY DATA WP channel type FP
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PRELIMINARY DATA WP channel type WP
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PRELIMINARY DATA SuperHyway bus ana
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PRELIMINARY DATA SuperHyway watchpo
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PRELIMINARY DATA Address comparison
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PRELIMINARY DATA Freezing bus maste
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PRELIMINARY DATA WP channel type PL
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Page 199 and 200: PRELIMINARY DATA External debug int
Page 201 and 202: PRELIMINARY DATA SHdebug link 201 3
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Page 219 and 220: PRELIMINARY DATA Debug tool reset/s
Page 225 and 226: PRELIMINARY DATA Trigger functions
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Page 239: PRELIMINARY DATA DBUS protocol 239
Page 243 and 244: PRELIMINARY DATA Scalable parameter
Page 253 and 254: PRELIMINARY DATA Debug register add
Page 265 and 266: PRELIMINARY DATA Index A Actions 13
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Page 269 and 270: PRELIMINARY DATA 269 158-160, 166-1
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