SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA
Debug protocols and interfaces 123
Common trace message fields
Common trace message fields
Field
Size
Header
bit
positions
Description
MESSAGE_TYPE 3-bits [2:0] Defines the basic contents of the debug message as
described in Section : First word of message on page 118.
Only field values of 0b010 (DTRC background trace
message) and 0b011 (DTRC trigger trace message)
relate to trace messages.
SOURCE_MODULE 3-bits [5:3] Defines the on-chip source module which provides the
information in the trace message a .
Value - Description
0: WPC (CPU watchpoint controller)
1: SuperHyway bus analyzer
2-7 - Reserved for watchpoint logic in additional CPU
cores or future accelerator modules.
EVENT_TYPE 5-bits [10:6] Defines the watchpoint channel in the source module
which generated the trace message. Refer to
Table 4.1.6: Trace message header fields on page 247 for
watchpoint channel numbers in the WPC and each of the
bus analyzers.
OVER_STALL 1-bit [11] This bit has two meanings depending on whether the
stall-mode field of DM.TRCTL selects CPU stall mode or
discard mode. See Table 31: DM.TRCTL definition on
page 97.
In stall mode, this bit is set when the CPU was stalled for
some indeterminate time prior to this trace message being
generated because there was no space available in the
debug module FIFO.
In discard mode, this bit is set to indicate that one or more
watchpoint hits before this hit were discarded because
there was no space available in the capture buffer.
D R A FT
Table 40: Common trace message fields
05-SA-10003 v1.0
SuperH, Inc.
SH-5 System Architecture, Volume 3: Debug