SuperH (SH) 64-bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA 74 Reset, panic and debug events 1.7.1 RESVEC/DBRVEC selection Note: By default, any occurrence of reset, panic or debug events will vector through RESVEC as defined in the instruction set architecture. The WPC provides two memory mapped registers which allow this behavior to be modified: • WPC.CPU_DBRVEC Defines a separate vector known as DBRVEC. The least significant bit of DBRVEC provides the same facilities as RESVEC in that it allows the MMU to be disabled when launching the DBRVEC handler in response to debug events (DEBUGIA, DEBUGIV, DEBUGOA, DEBUGSS, BREAK, PANIC and CPURESET). • WPC.CPU_DBRMODE Selects whether debug events vector through RESVEC or through DBRVEC. From the CPU core’s viewpoint, DEBUGRESET is indistinguishable from POWERON reset. Thus DEBUGRESET will always vector through RESVEC irrespective of the setting of WPC.CPU_DBRMODE.. WPC.CPU_DBRMODE WPC.CPU_DBRMODE 0x104008 Field Bits Size Volatile? Synopsis Type ENABLE 0 1 — DBRVEC enable RW Operation When read When written HARD reset 0 Selects whether RESVEC or DBRVEC is used for reset, panic and debug Events. Value - Description 0: Use RESVEC D R A FT 1: Use DBRVEC Returns current value Updates value Table 23: WPC.CPU_DBRMODE register definition SuperH, Inc. SH-5 System Architecture, Volume 3: Debug 05-SA-10003 v1.0
PRELIMINARY DATA Reset, panic and debug events 75 WPC.CPU_DBRMODE 0x104008 Field Bits Size Volatile? Synopsis Type — [63:1] 63 — Reserved RES Operation Reserved When read Returns 0 When written HARD reset 0 Ignored Table 23: WPC.CPU_DBRMODE register definition D R A FT 05-SA-10003 v1.0 SuperH, Inc. SH-5 System Architecture, Volume 3: Debug
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PRELIMINARY DATA SuperH TM (SH) 64-
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PRELIMINARY DATA Contents Preface 9
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PRELIMINARY DATA 5 1.8.11 DM.TRBUF
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PRELIMINARY DATA 7 3.2.5 Pin state
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PRELIMINARY DATA Preface This docum
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PRELIMINARY DATA Debug/trace archit
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PRELIMINARY DATA Overview of debug
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PRELIMINARY DATA Key concepts 15 Th
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PRELIMINARY DATA Key concepts 17 Ac
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PRELIMINARY DATA Key concepts 19 1.
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PRELIMINARY DATA Key concepts 21 1.
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PRELIMINARY DATA Debug protocols an
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PRELIMINARY DATA WP channel type BR
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PRELIMINARY DATA WP channel type IA
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PRELIMINARY DATA WP channel type IA
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PRELIMINARY DATA WP channel type OA
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PRELIMINARY DATA WP channel type IV
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PRELIMINARY DATA WP channel type IV
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PRELIMINARY DATA WP channel type FP
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PRELIMINARY DATA WP channel type WP
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PRELIMINARY DATA SuperHyway bus ana
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PRELIMINARY DATA SuperHyway watchpo
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PRELIMINARY DATA Address comparison
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PRELIMINARY DATA Freezing bus maste
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PRELIMINARY DATA WP channel type PL
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PRELIMINARY DATA External debug int
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PRELIMINARY DATA SHdebug link 201 3
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PRELIMINARY DATA SHdebug link 205 T
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PRELIMINARY DATA SHdebug link 207 D
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PRELIMINARY DATA JTAG interface 213
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PRELIMINARY DATA Debug tool reset/s
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PRELIMINARY DATA Trigger functions
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PRELIMINARY DATA DBUS protocol 227
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PRELIMINARY DATA Implementation spe
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PRELIMINARY DATA Scalable parameter
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PRELIMINARY DATA Debug register add
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PRELIMINARY DATA Index A Actions 13
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PRELIMINARY DATA 267 244, . . . . .
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PRELIMINARY DATA 269 158-160, 166-1
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