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Chapter 10 Memory Subsystem.pdf

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Public Version<br />

General-Purpose <strong>Memory</strong> Controller www.ti.com<br />

Bits Field Name Description Type Reset<br />

31:12 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00000<br />

11:8 MASKADDRESS CS mask address. RW 0xF<br />

0x0000: Chip-select size of 256 Mbytes<br />

0x<strong>10</strong>00: Chip-select size of 128 Mbytes<br />

0x1<strong>10</strong>0: Chip-select size of 64 Mbytes<br />

0x11<strong>10</strong>: Chip-select size of 32 Mbytes<br />

0x1111: Chip-select size of 16 Mbytes<br />

Other values must be avoided as they create holes in the<br />

chip-select address space.<br />

7 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x0<br />

6 CSVALID CS enable RW See (1)<br />

0x0: CS disabled<br />

0x1: CS enabled<br />

5:0 BASEADDRESS CSi base address (16M bytes minimum granularity) bits [5:0] RW 0x00<br />

corresponds to A29, A28, A27, A26, A25, and A24. See<br />

Figure <strong>10</strong>-6<br />

(1) Reset value is 0x1 for CS0 and 0x0 for CS1 to CS7<br />

Table <strong>10</strong>-62. Register Call Summary for Register GPMC_CONFIG7_i<br />

General-Purpose <strong>Memory</strong> Controller<br />

• Chip-Select Base Address and Region Size Configuration: [0] [1] [2]<br />

• NAND Device Basic Programming Model: [3]<br />

• GPMC Register Summary: [4]<br />

Table <strong>10</strong>-63. GPMC_NAND_COMMAND_i<br />

Address Offset 0x0000 007C + (0x0000 0030 * i) Index i = 0 to 7<br />

Physical Address 0x6E00 007C + (0x0000 0030 * i) Instance GPMC<br />

Description This register is not a true register, just an address location.<br />

Type W<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 <strong>10</strong> 9 8 7 6 5 4 3 2 1 0<br />

GPMC_NAND_COMMAND<br />

Bits Field Name Description Type Reset<br />

31:0 GPMC_NAND_COMMAND This register is not a true register, just an address W n/a<br />

location.<br />

Table <strong>10</strong>-64. Register Call Summary for Register GPMC_NAND_COMMAND_i<br />

General-Purpose <strong>Memory</strong> Controller<br />

• NAND Device Basic Programming Model: [0] [1] [2] [3] [4] [5] [6]<br />

• GPMC Register Summary: [7]<br />

Table <strong>10</strong>-65. GPMC_NAND_ADDRESS_i<br />

Address Offset 0x0000 0080 + (0x0000 0030 * i) Index i = 0 to 7<br />

Physical Address 0x6E00 0080 + (0x0000 0030 * i) Instance GPMC<br />

Description This register is not a true register, just an address location.<br />

Type W<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 <strong>10</strong> 9 8 7 6 5 4 3 2 1 0<br />

GPMC_NAND_ADDRESS<br />

2194 <strong>Memory</strong> <strong>Subsystem</strong> SPRUGN4L–May 20<strong>10</strong>–Revised June 2011<br />

Copyright © 20<strong>10</strong>–2011, Texas Instruments Incorporated

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