Chapter 10 Memory Subsystem.pdf

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www.ti.com SDRAM Controller (SDRC) Subsystem
It is assumed that the system interconnect on which the SMS is plugged is responsible for signaling the
error event to the host MPU based on the interconnect response. The MPU error handler can then consult
the error logging registers.
10.2.5.2 SDRC Configuration
10.2.5.2.1 IP Revision
The IP revision code can be read in the SDRC.SDRC_REVISION[7:0] REV field.
10.2.5.2.2 Reset Behavior
The reset behavior of the SDRC can be classified into three subgroups:
• Asynchronous cold-reset (power-on reset) behavior
• Asynchronous warm reset behavior
• Synchronous soft-reset behavior
When the system-wide power-on reset is applied through cold reset, all flops are reset to their default
values, and all state-machines are returned to their idle states.
The programming model for data recovery following a warm reset is as follows:
• Program the SDRC.SDRC_POWER_REG register to enable the SDRC.SDRC_POWER_REG[7]
SRFRONRESET bit.
A warm reset condition is then issued.
• The SDRC enters self-refresh mode since the SRFRONRESET bit is set.
• The SDRC does not execute global SDRC reset since the reset is not qualified as cold.
• The SDRC state-machine maintains the external memory device in self-refresh.
The first SDRC access to the configuration register must then be:
1. Check the SDRC configuration.
2. Exit self-refresh mode using the manual command register.
A software-controlled reset is also available by using the SDRC.SDRC_SYSCONFIG[1] SOFTRESET bit
(set this bit to 1 to activate the reset). The completion of the reset can be determined by reading the
SDRC.SDRC_SYSSTATUS[0] RESETDONE bit.
When the SDRC is reset due to the presence of either a soft or cold reset, all SDRC flops are reset.
NOTE: SDRC Requirement at First Power-Up to Have sdrc_cke Pin High
To comply with the JEDEC standard, sdrc_cke pins values are forced to 1 during the initial
memory power-up phase: software must ensure that sdrc_cke pin is released after the
initialization phase; it happens only at first power-up (on a cold reset). Thus, at the end of the
initial SDRC power-up sequence and before programing the PWDENA field, software must
ensure that the sdrc_cke pin is driven by the SDRC module. Then the value of the PWDENA
field can be modified. See Section 10.2.5.4.1 for more details on sdrc_cke driving.
NOTE: Set the INPUTENABLE0 bit of CONTROL.CONTROL_PADCONF_SDRC_CLK to assure
the synchronization of sdrc_clk. For more information, see Chapter 13, System Control
Module.
10.2.5.3 SDRC Setup
A number of device parameters must be set before executing the initialization sequence.
SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem
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