Chapter 10 Memory Subsystem.pdf

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General-Purpose Memory Controller www.ti.com
Bits Field Name Description Type Reset
31:21 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x000
20:16 ADVWROFFTIME nADV de-assertion time from start cycle time for write accesses RW 0x02
0x00: 0 GPMC_FCLK cycle
0x01: 1 GPMC_FCLK cycle
...
0x1F: 31 GPMC_FCLK cycles
15:13 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0
12:8 ADVRDOFFTIME nADV de-assertion time from start cycle time for read accesses RW 0x02
0x00: 0 GPMC_FCLK cycle
0x01: 1 GPMC_FCLK cycle
...
0x1F: 31 GPMC_FCLK cycles
7 ADVEXTRADELAY nADV Add Extra Half GPMC_FCLK cycle RW 0x0
0x0: nADV Timing control signal is not delayed
0x1: nADV Timing control signal is delayed of half GPMC_FCLK
clock cycle
6:4 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0
3:0 ADVONTIME nADV assertion time from start cycle time RW 0x1
0x0: 0 GPMC_FCLK cycle
0x1: 1 GPMC_FCLK cycle
...
0xF: 15 GPMC_FCLK cycles
Table 10-54. Register Call Summary for Register GPMC_CONFIG3_i
General-Purpose Memory Controller
• Timing Setting: [0] [1] [2] [3]
• Asynchronous Access Description: [4] [5] [6] [7] [8] [9]
• Synchronous Access: [10] [11] [12] [13] [14] [15]
• GPMC Register Summary: [16]
Table 10-55. GPMC_CONFIG4_i
Address Offset 0x0000 006C + (0x0000 0030 * i) Index i = 0 to 7
Physical Address 0x6E00 006C + (0x0000 0030 * i) Instance GPMC
Description nWE and nOE signals timing parameter configuration
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
WEOFFTIME WEONTIME OEOFFTIME OEONTIME
WEEXTRADELAY
RESERVED
Bits Field Name Description Type Reset
31:29 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0
28:24 WEOFFTIME nWE de-assertion time from start cycle time RW 0x10
0x00: 0 GPMC_FCLK cycle
0x01: 1 GPMC_FCLK cycle
...
0x1F: 31 GPMC_FCLK cycles
23 WEEXTRADELAY nWE Add Extra Half GPMC_FCLK cycle RW 0x0
RESERVED
0x0: nWE Timing control signal is not delayed
0x1: nWE Timing control signal is delayed of half GPMC_FCLK
clock cycle
2190 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011
Copyright © 2010–2011, Texas Instruments Incorporated
OEEXTRADELAY
RESERVED