Chapter 10 Memory Subsystem.pdf

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Public Version SDRAM Controller (SDRC) Subsystem www.ti.com SDRAM Controller (SDRC) Subsystem • Firewalls: [0] [1] [2] [3] [4] [5] • SMS Firewall Usage: [6] • SMS Register Summary: [7] Table 10-120. Register Call Summary for Register SMS_RG_ATTi Table 10-121. SMS_RG_RDPERMi Address Offset 0x0000 0050 + (0x0000 0020 * i) Index i = 0 to 7 Physical Address 0x6C00 0050 + (0x0000 0020 * i) Instance SMS Description This register provides the list of all initiators that have permission for reading from that memory region. Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CONNIDVECTOR Bits Field Name Description Type Reset 31:16 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0000 15:0 CONNIDVECTOR One bit per initiator group. Bit 0 set to 1 means that initiator whose RW 0x---- (1) ConnID = 0 has read permission to the protected region i. (1) Reset value exported from control module for region 0 and region 1; reset value equal to 0x0000 for other Table 10-122. Register Call Summary for Register SMS_RG_RDPERMi SDRAM Controller (SDRC) Subsystem • Firewalls: [0] • SMS Firewall Usage: [1] • SMS Register Summary: [2] Table 10-123. SMS_RG_WRPERMi Address Offset 0x0000 0058 + (0x0000 0020 * i) Index i = 0 to 7 Physical Address 0x6C00 0058 + (0x0000 0020 * i) Instance SMS Description This register provides the list of all initiators that have permission for writing to that memory region. Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CONNIDVECTOR Bits Field Name Description Type Reset 31:16 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0000 15:0 CONNIDVECTOR One bit per initiator group. Bit 0 set to 1 means that initiator RW 0x---- (1) whose ConnID = 0 has write permission to the protected region i. (1) Reset value exported from control module for region 0 and region 1; reset value equal to 0x0000 for other Table 10-124. Register Call Summary for Register SMS_RG_WRPERMi SDRAM Controller (SDRC) Subsystem • Firewalls: [0] • SMS Firewall Usage: [1] • SMS Register Summary: [2] 2286Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated
Public Version www.ti.com SDRAM Controller (SDRC) Subsystem Table 10-125. SMS_RG_STARTj Address Offset 0x0000 0060 + (0x0000 0020 * (k)) Index j = 1 to 7 and k = 0 to 8 Physical Address 0x6C00 0060 + (0x0000 0020 * (k)) Instance SMS Description This register provides the region #j start address (lowest address inside the region), with a 64-KB granularity. Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED STARTADDRESS RESERVED Bits Field Name Description Type Reset 31 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x0 30:16 STARTADDRESS Region #j start address (included in the region) RW 0x---- Aligned on 64-KB boundary. [15:0] must be written with 0s. No STARTADDRESS parameter for region 0. 15:0 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x0000 SDRAM Controller (SDRC) Subsystem • SMS Firewall Usage: [0] [1] • SMS Register Summary: [2] Table 10-126. Register Call Summary for Register SMS_RG_STARTj Table 10-127. SMS_RG_ENDj Address Offset 0x0000 0064 + (0x0000 0020 * (K)) Index j = 1 to 7 and k = 0 to 8 Physical Address 0x6C00 0064 + (0x0000 0020 * (K)) Instance SMS Description This register provides the region #j end address (lowest address outside the region), with a 64-KB granularity. Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED ENDADDRESS RESERVED Bits Field Name Description Type Reset 31 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0 30:16 ENDADDRESS Region #j end address (not included in the region) RW 0x---- Aligned on 64-KB boundary. [15:0] must be written with 0s. No ENDADDRESS parameter for region 0. 15:0 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0000 SDRAM Controller (SDRC) Subsystem • SMS Firewall Usage: [0] [1] • SMS Register Summary: [2] Table 10-128. Register Call Summary for Register SMS_RG_ENDj SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem2287 Copyright © 2010–2011, Texas Instruments Incorporated
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This chapter describes the memory s
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Device GPMC External device/ memory
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Public Version www.ti.com General-P
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1 GBytes 512 MBytes 256 MBytes 128
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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nCS nBE0/CLE nWE nADV/ALE CSONTIME=
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nCS nBE0/CLE nWE Public Version www
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Row 0 Row 1 Row 2 Row 3 Row 252 Row
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512 Bytes input Row 0 Row 1 Row 2 R
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M0 Manual mode Rd/Wr/ SW Mode Size0
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M1 M2 M3 M4 Per-sector spares Spare
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M9 Per-sector spares, separate ECC
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GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
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Device GPMC module A [27:17] A [16:
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FCLK CLK nADV nCS nOE A/D bus ClkAc
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FCLK nCS nADV nWE A/D bus AdvWrOffT
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Public Version www.ti.com SDRAM Con
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Device SDRAM controller subsystem R
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MUX1 System address 31 30 29 28 27
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MUX23 System address Address mappin
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Configuration register file Rotatio
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Level 0 Region 0 Public Version www
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OCP slave interface OCP slave port
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BANKALLOCATION = 0b00 BANKALLOCATIO
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Page 143 and 144: Endianism CSnMUXCFG field SDRC.SDRC
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