Chapter 10 Memory Subsystem.pdf

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Device SDRAM controller subsystem Retiming sdrc_nras sdrc_ncas sdrc_ncs[1:0] sdrc_cke0 sdrc_nclk sdrc_a[14:0] sdrc_nwe sdrc_ba[1:0] sdrc_dm[3:0] sdrc_dqs[3:0] sdrc_d[15:0] sdrc_d[31:16] sdrc_cke1 sdrc_clk I/O configuration logic System control module INPUTENABLE bit Public Version SDRAM Controller (SDRC) Subsystem www.ti.com 10.2.2 SDRC Subsystem Environment 10.2.2.1 SDRC Subsystem Description Figure 10-42 shows the SDRC subsystem interfacing with one 16- and one 32-bit SDR external memories. Figure 10-43 shows the SDRC subsystem interfacing with one 16- and one 32-bit DDR memories. Figure 10-42. SDRC Subsystem Connections to SDR SDRAM x16 SDR SDRAM nRAS nCAS nCS(0) CKE CLK addr[14:0] nWE BA[1:0] DQMH DQML DQ[15:0] x32 SDR SDRAM nRAS nCAS nCS(1) CKE CLK addr[14:0] nWE BA[1:0] DQ[15:0] DQ[31:16] DQM[1:0] 2208 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated sdrc-002
Device SDRAM controller subsystem Retiming sdrc_nras sdrc_ncas sdrc_ncs[1:0] sdrc_cke0 sdrc_nclk sdrc_a[14:0] sdrc_nwe sdrc_ba[1:0] sdrc_dm[3:0] sdrc_dqs[3:0] sdrc_d[15:0] sdrc_d[31:16] sdrc_cke1 sdrc_clk I/O configuration logic System control module INPUTENABLE bit Public Version www.ti.com SDRAM Controller (SDRC) Subsystem Figure 10-43. SDRC Subsystem Connections to DDR SDRAM CAUTION nRAS nCAS nCS(0) CKE CLK nCLK x16 DDR SDRAM addr[14:0] nWE BA[1:0] DM[1:0] DQS[1:0] DQ[15:0] nRAS nCAS nCS(1) CKE CLK nCLK x32 DDR SDRAM addr[14:0] nWE BA[1:0] DQS[3:0] DQ[15:0] DQ[31:16] DM[3:0] Both memory types (SRD/DDR SDRAM) cannot be connected simultaneously to the SDRC memory interface. Table 10-95 lists SDRC subsystem I/O pins. Table 10-95. SDRC Subsystem I/O Description Pin Type Description sdrc_d[31:0] I/O 32-bit wide data bus sdrc_ba[1:0] O Bank address 1-0 sdrc_a[14:0] O Address bus SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated sdrc-003 2209
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This chapter describes the memory s
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Device GPMC External device/ memory
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Public Version www.ti.com General-P
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1 GBytes 512 MBytes 256 MBytes 128
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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nCS nBE0/CLE nWE nADV/ALE CSONTIME=
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nCS nBE0/CLE nWE Public Version www
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Row 0 Row 1 Row 2 Row 3 Row 252 Row
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512 Bytes input Row 0 Row 1 Row 2 R
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M0 Manual mode Rd/Wr/ SW Mode Size0
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Page 65 and 66: M1 M2 M3 M4 Per-sector spares Spare
Page 67 and 68: M9 Per-sector spares, separate ECC
Page 73 and 74: GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
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Page 77 and 78: FCLK CLK nADV nCS nOE A/D bus ClkAc
Page 79 and 80: FCLK nCS nADV nWE A/D bus AdvWrOffT
Page 111 and 112: Public Version www.ti.com SDRAM Con
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Page 119 and 120: MUX1 System address 31 30 29 28 27
Page 121 and 122: MUX23 System address Address mappin
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Page 131 and 132: Level 0 Region 0 Public Version www
Page 135 and 136: OCP slave interface OCP slave port
Page 139 and 140: BANKALLOCATION = 0b00 BANKALLOCATIO
Page 143 and 144: Endianism CSnMUXCFG field SDRC.SDRC
Page 149 and 150: CLK CMD WRITE DQ DQS CLK CMD DQ DQS
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Public Version www.ti.com SDRAM Con
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8 bits 32 bits Y0 U Y1 V P0 P1 16 b
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Start configuration of VRFB context
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Initiator: Camera subsystem SDRC Su
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Request for transaction on class 1
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Class 1 and class 2 request for tra
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No A Class 0 empty? Yes Class 1 emp
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Status: There are n pending request
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4 GB 0x0000 0000 0x6C00 0000 0x6CFF
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Device D2D OCM_ROM OCM_RAM ROM (32K
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Public Version www.ti.com On-Chip M
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