Chapter 10 Memory Subsystem.pdf

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Table 10-24. Supported Memory Interfaces (continued)
16-Bit Address/Data Muxed
Function OneNAND 16-bit NAND 8-bit NAND
pSRAM or NOR Flash (1)
GPMC_ncs3 nCS3 nCE3
GPMC_ncs4 nCS4 nCE4
GPMC_ncs5 nCS5 nCE5
GPMC_ncs6 nCS6 nCE6
GPMC_ncs7 nCS7 nCE7
gpmc_nadv_ale nADV (address valid) ALE (address latch enable)
gpmc_noe nOE (output enable) nRE (read enable)
gpmc_nwe nWE (write enable) nWE (write enable)
gpmc_nbe0_cle nBE0 (byte enable) CLE (command latch enable)
gpmc_nbe1 nBE1
gpmc_nwp nWP (write protect) nWP (write protect)
gpmc_wait0 WAIT0 R/nB0 (ready/busy)
gpmc_wait1 WAIT1 R/nB1
gpmc_wait2 WAIT2 R/nB2
gpmc_wait3 WAIT3 R/nB3
10.1.6.2.1.2 NAND Interface Protocol
NAND flash architecture, introduced in 1989, is a flash technology. NAND is a page-oriented memory
device (that is, read and write accesses are done by pages). NAND achieves density by sharing common
areas of the storage transistor, which creates strings of serially connected transistors (in NOR devices,
each transistor stands alone). Because of its high density, NAND is best suited to devices requiring high
capacity data storage, such as pictures, music, or data files. Because of its nonvolatility, NAND is a good
storage solution for many applications where mobility, low power, and speed are key factors. Low pin
count and simple interface are other advantages of NAND.
Table 10-25 summarizes the level of the NAND interface signals applied to external devices or memories.
Table 10-25. NAND Interface Bus Operations Summary
Bus operation CLE ALE nCE nWE (1) nRE (1) nWP
Read (cmd input) H L L RE H x
Read (add input) L H L RE H x
Write (cmd input) H L L RE H H
Write (add input) L H L RE H H
Data input L L L RE H H
Data output L L L H FE x
Busy (during read) x x H (2) H (2) H (2) x
Busy (during program) x x x x x H
Busy (during erase) x x x x x H
Write protect x x x x x L
Stand-by x x H x x H/L (3)
(1) RE stands for rising edge, FE stands for falling edge.
(2) Can be either nCE high, or WE and nRE high
(3) nWP must be biased to CMOS high or CMOS low for standby.
10.1.6.2.1.3 NOR Interface Protocol
NOR flash architecture, introduced in 1988, is a flash technology. Unlike NAND, which is a sequential
access device, NOR is directly addressable (that is, it is designed to be a random access device). NOR is
best suited to devices used to store and run code or firmware, usually in small capacities. While NOR has
fast read capabilities, it has slow write and erase functions compared to NAND architecture.
SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem
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