Chapter 10 Memory Subsystem.pdf

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SDRAM Controller (SDRC) Subsystem www.ti.com
Table 10-97. SDRC Address Multiplexing Scheme Selection vs SDRAM Configurations (x32
Memory Interface) (continued)
x32 Memory Interface
Banks Column Row MUX Total Size Number of Device
Address Address Scheme (MBits) Devices Organization
BA1, 2 A0-A9 10 A0-A11 12 MUX11 512 4 16M x 8
BA0
2 16M x 16
1 16M x 32
BA1, 2 A0-A9 10 A0-A12 13 MUX14 1024 4 32M x 8
BA0
2 32M x 16
1 32M x 32
BA1, 2 A0-A9 10 A0-A13 14 MUX16 2048 2 64M x 16
BA0
1 64M x 32
BA1, 2 A0-A9 10 A0-A14 15 MUX29 4096 1 128M x 32
BA0
BA1, 2 A0-A9; A11 11 A0-A12 13 MUX15 2048 4 64M x 8
BA0
2 64M x 16
1 64M x 32
Table 10-96 is valid per CS (in the table, the total size in Mbits corresponds to a single CS). Both chips
must use the same address scheme, but can use different address multiplexing configurations.
Figure 10-44 through Figure 10-46 show all the SDRAM MUX schemes, including the mapping of the
32-bit system address of the column and row addresses of the memory device.
NOTE: The bank-select bit (BA1) does not exist for 2-bank devices.
2212 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011
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