Chapter 10 Memory Subsystem.pdf

Device
MPU subsystem DMA subsystem
On-chip
memory
(RAM/
ROM)
Public Version
General-Purpose Memory Controller www.ti.com
10.1 General-Purpose Memory Controller
10.1.1 General-Purpose Memory Controller Overview
The general-purpose memory controller (GPMC) is the device unified memory controller (UMC) dedicated
to interfacing external memory devices:
• Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices
• Asynchronous, synchronous, and page mode burst NOR flash devices
• NAND flash
• Pseudo-SRAM devices
Figure 10-1 shows the environment of the GPMC.
10.1.1.1 GPMC Features
Figure 10-1. GPMC Environment
L3 Interconnect L3 interconnect
SDRAM controller subsystem
SDRAM Memory
Scheduler
SDRC
Other
master
cores
GPMC
SDRAM NOR, NAND
flash
gpmc−001
The GPMC is the device 16-bit external memory controller. The GPMC data access engine provides a
flexible programming model for communication with all standard memories. The GPMC supports various
accesses:
• Asynchronous read/write access
• Asynchronous read page access (4, 8, 16 Word16)
2096 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011
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