Chapter 10 Memory Subsystem.pdf

GPMC_FCLK
GPMC_CLK
gpmc_a[11:1]
(connected to A [26:17] on memory side)
gpmc_d[15:0]
(connected to A [16:1] / D [15:0] on
memory side)
nBE1/nBE0
nCS
nADV
nWE
DIR
WAIT
CSONTIME
Valid Address
WRDATAONADMUXBUS
Valid Address Data
CSWROFFTIME
ADVWROFFTIME
ADVONTIME
WEOFFTIME
WEONTIME
Public Version
General-Purpose Memory Controller www.ti.com
• Total access time (GPMC.GPMC_CONFIG5_i[4:0] RDCYCLETIME) corresponds to RDACCESSTIME
plus the address hold time from nCS deassertion, plus time from RDACCESSTIME to
CSWROFFTIME.
• Direction signal DIR:
DIR goes from OUT to IN at the same time as nOE assertion.
After a read operation, if no other access (read or write) is pending, the data bus is driven with the
previous read value. See Section 10.1.5.3.10, Bus Keeping Support.
10.1.5.10.2 Synchronous Single Write
Figure 10-17. Synchronous Single Write on an Address/Data-Multiplexed Device
NOTE: The WAIT signal is active low.
WRCYCLETIME
When the GPMC generates a write access to an address/data-multiplexed device, it drives the data bus
until WRDATAONADMUXBUS time (GPMC_CONFIG6_i[19:16]).
The GPMC.GPMC_CONFIG1_i register settings (i = 0 to 7) are as follows:
OUT
• WRITEMULTIPLE bit at 0 (write single access)
• WRITETYPE bit at 1 (write synchronous)
• MUXADDDATA bit at 1 (address/data-multiplexed device)
Address bits [16:1] are placed on the address/data bus at cycle-start time, and the remaining address bits
[26:17] are placed on the address bus.
The address phase ends at WRDATAONADMUXBUS.
The nCS, nADV, and nWE signals are controlled in the same way as nonmultiplexed accesses.
First data of the burst is driven on the address/data bus at WRDATAONADMUXBUS time.
2132 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011
Copyright © 2010–2011, Texas Instruments Incorporated
gpmc-017