Chapter 10 Memory Subsystem.pdf

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www.ti.com On-Chip Memory Subsystem
When the memory is not accessed by the system, the module performs automatic clock gating. Because
the clock to the memory is dynamically gated, there is no extra latency when the clock must be switched
on after an idle state.
10.3.2.2.2 Hardware Reset
Global reset of the module is performed by activation of the CORE_RST in the core reset domain (see
Chapter 3, Power, Reset, and Clock Management.).
10.3.2.2.3 Power Domain
OCM power is supplied by the CORE power domain (see Chapter 3, Power, Reset, and Clock
Management).
10.3.3 OCM Subsystem Functional Description
10.3.3.1 OCM_ROM
The embedded ROM is used primarily for booting, flashing, and context restoring.
The device-embedded ROM (total 32K bytes) has the following characteristics:
• The OCM_ROM is always accessible, and contains the boot area.
• The OCM_ROM supports single and burst access transactions.
• The OCM_ROM operates at full interconnect clock frequency.
• The COM_ROM needs three cycles for initial access and one cycle per subsequent access.
The memory space of the embedded ROM starts at 0x4001 4000 and ends at 0x4001 BFFF.
10.3.3.2 OCM_RAM
By default, only 2K bytes are available after reset; however, the configuration can then be changed to
adapt to booting/flashing, normal boot, or to any application requirement.
The device-embedded RAM has the following characteristics:
• Operates at full L3 interconnect clock frequency
• Fully pipelined, one 32-bit access per cycle
• Restricted access support, based on:
– A region-based partitioning (see the L3 firewall description)
– The module owner of the access, with respect to its read and write permission to that region
– The transaction attributes of the access, with respect to the region permission properties:
• User/supervisor
• Code/data access
The OCM_RAM can be partitioned using the L3 firewall and used as RAM for a video frame buffer or to
any application.
The RAM memory space starts at 0x4020 0000 and ends at 0x4020 FFFF.
SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem
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