Chapter 10 Memory Subsystem.pdf

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Public Version General-Purpose Memory Controller www.ti.com Table 10-78. Register Call Summary for Register GPMC_ECC_CONFIG General-Purpose Memory Controller • Error correction code engine (ECC): [0] [1] • NAND Device Basic Programming Model: [2] [3] [4] [5] [6] [7] [8] [9] • GPMC Register Summary: [10] • GPMC Register Description: [11] [12] [13] Address Offset 0x0000 01F8 Table 10-79. GPMC_ECC_CONTROL Physical Address 0x6E00 01F8 Instance GPMC Description ECC control Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED ECCPOINTER Bits Field Name Description Type Reset 31:9 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x000000 8 ECCCLEAR Clear all ECC result registers RW 0x0 Reads returns 0 Write 0x1 to this field clear all ECC result registers Write 0x0 is ignored 7:4 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0 3:0 ECCPOINTER Selects ECC result register (Reads to this field give the dynamic RW 0x0 position of the ECC pointer - Writes to this field select the ECC result register where the first ECC computation will be stored); Other enums: writing other values disables the ECC engine (ECCENABLE bit of GPMC_ECC_CONFIG set to 0) 0x0: Writing 0x0 disables the ECC engine (ECCENABLE bit of GPMC_ECC_CONFIG set to 0) 0x1: ECC result register 1 selected 0x2: ECC result register 2 selected 0x3: ECC result register 3 selected 0x4: ECC result register 4 selected 0x5: ECC result register 5 selected 0x6: ECC result register 6 selected 0x7: ECC result register 7 selected 0x8: ECC result register 8 selected 0x9: ECC result register 9 selected Table 10-80. Register Call Summary for Register GPMC_ECC_CONTROL General-Purpose Memory Controller • NAND Device Basic Programming Model: [0] [1] [2] [3] • GPMC Register Summary: [4] 2200 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated ECCCLEAR
Public Version www.ti.com General-Purpose Memory Controller Address Offset 0x0000 01FC Table 10-81. GPMC_ECC_SIZE_CONFIG Physical Address 0x6E00 01FC Instance GPMC Description ECC size Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED ECCSIZE1 ECCSIZE0 RESERVED Bits Field Name Description Type Reset 31:30 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0 29:22 ECCSIZE1 Defines ECC size 1 RW 0xFF 0x00: 2 Bytes 0x01: 4 Bytes 0x02: 6 Bytes 0x03: 8 Bytes ... 0xFF: 512 Bytes 21:20 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0 19:12 ECCSIZE0 Defines ECC size 0 RW 0xFF 0x00: 2 Bytes 0x01: 4 Bytes 0x02: 6 Bytes 0x03: 8 Bytes ... 0xFF: 512 Bytes 11:9 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0 8 ECC9RESULTSIZE Selects ECC size for ECC 9 result register RW 0x0 0x0: ECCSIZE0 selected 0x1: ECCSIZE1 selected 7 ECC8RESULTSIZE Selects ECC size for ECC 8 result register RW 0x0 0x0: ECCSIZE0 selected 0x1: ECCSIZE1 selected 6 ECC7RESULTSIZE Selects ECC size for ECC 7 result register RW 0x0 0x0: ECCSIZE0 selected 0x1: ECCSIZE1 selected 5 ECC6RESULTSIZE Selects ECC size for ECC 6 result register RW 0x0 0x0: ECCSIZE0 selected 0x1: ECCSIZE1 selected 4 ECC5RESULTSIZE Selects ECC size for ECC 5 result register RW 0x0 0x0: ECCSIZE0 selected 0x1: ECCSIZE1 selected 3 ECC4RESULTSIZE Selects ECC size for ECC 4 result register RW 0x0 0x0: ECCSIZE0 selected 0x1: ECCSIZE1 selected 2 ECC3RESULTSIZE Selects ECC size for ECC 3 result register RW 0x0 0x0: ECCSIZE0 selected 0x1: ECCSIZE1 selected SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem RESERVED Copyright © 2010–2011, Texas Instruments Incorporated ECC9RESULTSIZE ECC8RESULTSIZE ECC7RESULTSIZE ECC6RESULTSIZE ECC5RESULTSIZE ECC4RESULTSIZE ECC3RESULTSIZE ECC2RESULTSIZE ECC1RESULTSIZE 2201
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This chapter describes the memory s
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Device GPMC External device/ memory
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Public Version www.ti.com General-P
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1 GBytes 512 MBytes 256 MBytes 128
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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nCS nBE0/CLE nWE nADV/ALE CSONTIME=
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nCS nBE0/CLE nWE Public Version www
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Row 0 Row 1 Row 2 Row 3 Row 252 Row
Page 55 and 56: 512 Bytes input Row 0 Row 1 Row 2 R
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Page 61 and 62: M0 Manual mode Rd/Wr/ SW Mode Size0
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Page 67 and 68: M9 Per-sector spares, separate ECC
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Page 75 and 76: Device GPMC module A [27:17] A [16:
Page 77 and 78: FCLK CLK nADV nCS nOE A/D bus ClkAc
Page 79 and 80: FCLK nCS nADV nWE A/D bus AdvWrOffT
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Page 121 and 122: MUX23 System address Address mappin
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Page 135 and 136: OCP slave interface OCP slave port
Page 139 and 140: BANKALLOCATION = 0b00 BANKALLOCATIO
Page 143 and 144: Endianism CSnMUXCFG field SDRC.SDRC
Page 149 and 150: CLK CMD WRITE DQ DQS CLK CMD DQ DQS
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Public Version www.ti.com SDRAM Con
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8 bits 32 bits Y0 U Y1 V P0 P1 16 b
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Start configuration of VRFB context
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Initiator: Camera subsystem SDRC Su
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Request for transaction on class 1
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Class 1 and class 2 request for tra
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No A Class 0 empty? Yes Class 1 emp
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Status: There are n pending request
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4 GB 0x0000 0000 0x6C00 0000 0x6CFF
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Device D2D OCM_ROM OCM_RAM ROM (32K
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Public Version www.ti.com On-Chip M
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