Chapter 10 Memory Subsystem.pdf

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Public Version SDRAM Controller (SDRC) Subsystem www.ti.com Table 10-156. Register Call Summary for Register SDRC_SYSCONFIG SDRAM Controller (SDRC) Subsystem • Software Reset: [0] • System Power Management: [1] • Reset Behavior: [2] • Mode Register Programming and Modes of Operation: [3] • SDRC Register Summary: [4] Address Offset 0x0000 0014 Table 10-157. SDRC_SYSSTATUS Physical Address 0x6D00 0014 Instance SDRC Description This register provides module status, excluding interrupt status info. Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED Bits Field Name Description Type Reset 31:8 RESERVED Reserved for module-specific status information R 0x000000 Read returns 0. 7:1 RESERVED Reserved for interconnect socket status information R 0x00 Read returns 0. 0 RESETDONE Internal reset monitoring R 0x- 0x0: Internal module reset is ongoing 0x1: Reset completed - The module is ready to be used Table 10-158. Register Call Summary for Register SDRC_SYSSTATUS SDRAM Controller (SDRC) Subsystem • Reset Behavior: [0] • SDRC Register Summary: [1] Address Offset 0x0000 0040 Table 10-159. SDRC_CS_CFG Physical Address 0x6D00 0040 Instance SDRC Description This register configures the start address of CS1 address space. Must be aligned on a boundary that is a multiple of the size of the attached memory, or of the next power of two if the memory size is not a power of two. Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED 2298 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated CS1STARTLOW CS1STARTHIGH RESETDONE
Public Version www.ti.com SDRAM Controller (SDRC) Subsystem Bits Field Name Description Type Reset 31:10 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x000000 9:8 CS1STARTLOW CS1 address space start address (lower add bits a1:a0) / 32MB unit RW 0x0 7:4 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x0 3:0 CS1STARTHIGH CS1 address space start address (upper add bits a5:a4:a3:a2) / 128MB RW 0x4 unit Table 10-160. Register Call Summary for Register SDRC_CS_CFG SDRAM Controller (SDRC) Subsystem • CS0-CS1 Memory Spaces: [0] [1] [2] [3] [4] • Chip-Select Configuration: [5] [6] • CS Memory Spaces: [7] [8] [9] [10] [11] [12] [13] • SDRC Register Summary: [14] Address Offset 0x0000 0044 Table 10-161. SDRC_SHARING Physical Address 0x6D00 0044 Instance SDRC Description This register specifies the SDRC attached memory size and position on the SDRC IOs. Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED LOCK RESERVED RESERVED Bits Field Name Description Type Reset 31 RESERVED Write 0s for future compatibility. RW 0x0 Read returns 0. 30 LOCK Read-only access lock bit RW See (1) 0x0: This register is fully writable. 0x1: When this bit is set, the register can not be unset until next reset of the module. 29:15 RESERVED Write 0s for future compatibility. RW See (1) Read returns 0s. 14:12 CS1MUXCFG Identifies the SDRC pins used by CS1 RW See (1) 0x0: 32-bit SDRAM on Datalane[31:0] 0x1: 32-bit SDRAM on Datalane[31:0] 0x2: 16-bit SDRAM on Datalane[31:16] 0x3: 16-bit SDRAM on Datalane[16:0] 0x4: Reserved 0x5: Reserved 0x6: Reserved 0x7: 16-bit SDRAM on Datalane[31:16] (1) Reset value is copied from the system control module. See the note in Section 10.2.5.3.2 and Section 13.4.9, SDRC Registers, in Chapter 13, System Control Module. SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem CS1MUXCFG CS0MUXCFG Copyright © 2010–2011, Texas Instruments Incorporated SDRCTRISTATE 2299
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This chapter describes the memory s
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Device GPMC External device/ memory
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Public Version www.ti.com General-P
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1 GBytes 512 MBytes 256 MBytes 128
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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nCS nBE0/CLE nWE nADV/ALE CSONTIME=
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nCS nBE0/CLE nWE Public Version www
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Row 0 Row 1 Row 2 Row 3 Row 252 Row
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512 Bytes input Row 0 Row 1 Row 2 R
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M0 Manual mode Rd/Wr/ SW Mode Size0
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M1 M2 M3 M4 Per-sector spares Spare
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M9 Per-sector spares, separate ECC
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GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
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Device GPMC module A [27:17] A [16:
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FCLK CLK nADV nCS nOE A/D bus ClkAc
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FCLK nCS nADV nWE A/D bus AdvWrOffT
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Public Version www.ti.com SDRAM Con
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Device SDRAM controller subsystem R
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MUX1 System address 31 30 29 28 27
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MUX23 System address Address mappin
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Configuration register file Rotatio
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Level 0 Region 0 Public Version www
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OCP slave interface OCP slave port
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BANKALLOCATION = 0b00 BANKALLOCATIO
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Endianism CSnMUXCFG field SDRC.SDRC
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CLK CMD WRITE DQ DQS CLK CMD DQ DQS
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CLK_IN SIGNAL_IN MODEMAXDELAY Initi
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Page 167 and 168: 8 bits 32 bits Y0 U Y1 V P0 P1 16 b
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