Chapter 10 Memory Subsystem.pdf

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The same applies to successive accesses occurring during Word32 or burst accesses split into successive
single accesses when the single-access mode is used (GPMC_CONFIG1_i[30] READMULTIPLE = 0 or
GPMC_CONFIG1_i[28] WRITEMULTIPLE = 0).
All control signals are kept in their default states during these idle GPMC_FCLK cycles. This prevents
back-to-back accesses to the same chip-select without idle cycles between accesses.
10.1.5.4.6.3 Idle Cycles Between Accesses to Different Chip-Select (CYCLE2CYCLEDIFFCSEN,
CYCLE2CYCLEDELAY)
Because of the pipelined behavior of the system, successive accesses to different chip-selects can occur
back-to-back with no idle cycles between accesses. Depending on the control signals (nCS, nADV/ALE,
nBE0/CLE, nOE/RE, nWE) assertion and de-assertion timing parameters and on the IC timing
parameters, some control signals assertion times may overlap between the successive accesses to
different CS. Similarly, some control signals (WE, OE/RE) may not respect required transition times.
To work around the overlapping and to observe the required control-signal transitions, a minimum of
CYCLE2CYCLEDELAY inactive cycles is inserted between the access being initiated to this chip-select
and the previous access ending for a different chip-select. This applies to any type of access (read or
write).
If GPMC_CONFIG6_i[6] CYCLE2CYCLEDIFFCSEN is enabled, the chip-select access is delayed until
CYCLE2CYCLEDELAY cycles have expired since the end of a previous access to a different chip-select.
CYCLE2CYCLEDELAY count starts at CSRDOFFTIME/CSWROFFTIME completion. All control signals
are kept inactive during the idle GPMC_FCLK cycles.
NOTE: CYCLE2CYCLESAMECSEN and CYCLE2CYCLEDIFFCSEN should be set in the
GPMC_CONFIG6_i registers to insert idle cycles between accesses on this chip-select and
after accesses to a different chip-select, respectively.
The CYCLE2CYCLEDELAY delay runs in parallel with the BUSTURNAROUND delay.
BUSTURNAROUND is a timing parameter defined for the ending chip-select access,
whereas CYCLE2CYCLEDELAY is a timing parameter defined for starting chip-select
access. The effective minimum delay between successive accesses is based on the larger
delay timing parameter and on the access type combination, since bus turnaround does not
apply to all access types. See Section 10.1.5.4.6.1 for more details on bus turnaround.
Table 10-3 describes the configuration required for idle cycle insertion.
Table 10-3. Idle Cycle Insertion Configuration
1st BUSTURN Second Chip- Add/Data CYCLE2 CYCLE2 Idle Cycle Insertion
Access AROUND Access Select Multiplexed CYCLE CYCLE Between the Two
Type Timing Type SAMECSEN DIFFCSEN Accesses
Parameter Parameter Parameter
R/W = 0 R/W Any Any 0 x No idle cycles are inserted if the
two accesses are well pipelined.
R > 0 R Same Nonmuxed x 0 No idle cycles are inserted if the
two accesses are well pipelined.
R > 0 R Different Nonmuxed 0 0 BTA cycles are inserted.
R > 0 R/W Any Muxed 0 0 BTA cycles are inserted.
R > 0 W Any Any 0 0 BTA cycles are inserted.
W > 0 R/W Any Any 0 0 No idle cycles are inserted if the
two accesses are well pipelined.
R/W = 0 R/W Same Any 1 x CYCLE2CYCLEDELAY cycles
are inserted.
R/W = 0 R/W Different Any x 1 CYCLE2CYCLEDELAY cycles
are inserted.
SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem
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