Chapter 10 Memory Subsystem.pdf
Chapter 10 Memory Subsystem.pdf
Chapter 10 Memory Subsystem.pdf
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Level 0<br />
Region 0<br />
Public Version<br />
www.ti.com SDRAM Controller (SDRC) <strong>Subsystem</strong><br />
Figure <strong>10</strong>-49. Region Organization<br />
Level 1<br />
Level 2<br />
Region 1<br />
sdrc-009<br />
Region 0 (default region containing the whole memory space): Level 0<br />
Region 1 (allows dynamic reprogramming of regions): Level 2<br />
Regions 2-7 (protection regions): Level 1<br />
Region 1 has the highest priority to perform dynamic masking of other already-programmed regions when<br />
they are reprogrammed.<br />
Overlapping regions of the same priority level is forbidden and results in a violation when an access to the<br />
concerned region occurs. This violation is reported in the error-log register. Priority-level handling is done<br />
in the hardware; it does not involve any specific software development.<br />
All transactions are checked, including those the RE has processed.<br />
When detecting a violation on an incoming request, the SMS respects the response ordering within the<br />
faulty thread.<br />
A violation flag is raised internally and the MThreadID field is logged. Generation of the interconnect error<br />
response is then local to the SMS; the response buffer must be used to manage the potential response<br />
collision with regular SDRC responses.<br />
SPRUGN4L–May 20<strong>10</strong>–Revised June 2011 <strong>Memory</strong> <strong>Subsystem</strong><br />
Copyright © 20<strong>10</strong>–2011, Texas Instruments Incorporated<br />
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