Chapter 10 Memory Subsystem.pdf

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Public Version SDRAM Controller (SDRC) Subsystem www.ti.com Address Offset 0x0000 0150 Table 10-129. SMS_CLASS_ARBITER0 Physical Address 0x6C00 0150 Instance SMS Description This register controls the arbitration parameters between the class 0 request groups. Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BURST-COMPLETE RESERVED RESERVED RESERVED EXTENDEDGRANT Bits Field Name Description Type Reset 31:30 BURST-COMPLETE Delayed service until burst request complete BurstComplete[k], k= 6 RW 0x0 to 7 (BURST-COMPLETE[30] is for group number 6, BURST-COMPLETE[31] is for group number 7) 0x0: Group #k request to arbiter issued as soon as the first burst request is available 0x1: Group #k request to arbiter delayed until a complete burst transaction is buffered 29:24 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00 23:20 EXTENDEDGRANT Extended grant service inside a class RW 0x5 Vector specifying the number of consecutive services a group is granted. 2 bits per group ExtendedGrant[2*k+1,2*k], k = 6 to 7 (EXTENDEDGRANT[21:20] is for group number 6, EXTENDEDGRANT[23:22] is for group number 7) 0x1: 1 service for group #k when granted 0x2: 2 services for group #k when granted 0x3: 3 services for group #k when granted 19:8 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x000 7:6 HIGHPRIOVECTOR High-priority attribute inside a class RW 0x0 Vector allocating a higher priority to one of the class members. A single group may be given this attribute at a time. HighPrioVector[k], k= 6 to 7 (HIGHPRIOVECTOR[6] is for group number 6, HIGHPRIOVECTOR[7] is for group number 7) 0x0: Group #k has standard priority (LRU based). 0x1: Group #k has the highest priority over all other class members. 5:0 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00 Table 10-130. Register Call Summary for Register SMS_CLASS_ARBITER0 SDRAM Controller (SDRC) Subsystem • Arbitration Policy: [0] [1] • Internal Class Arbitration: [2] • Memory-Access Scheduler Configuration: [3] • SMS Register Summary: [4] 2288 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated HIGHPRIOVECTOR
Public Version www.ti.com SDRAM Controller (SDRC) Subsystem Address Offset 0x0000 0154 Table 10-131. SMS_CLASS_ARBITER1 Physical Address 0x6C00 0154 Instance SMS Description This register controls the arbitration parameters between the class 1 request groups. Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED RESERVED BURST-COMPLETE Bits Field Name Description Type Reset 31:26 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00 25:24 BURST-COMPLETE Delayed service until burst request complete RW 0x0 BurstComplete[k], k= 0 to 1 (BURST-COMPLETE[24] is for group number 0, BURST-COMPLETE[25] is for group number 1) 0x0: Group #k request to arbiter issued as soon as the first burst request is available 0x1: Group #k request to arbiter delayed until a complete burst transaction is buffered 23:12 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x000 11:8 EXTENDEDGRANT Extended grant service inside a class RW 0x5 Vector specifying the number of consecutive services a group is granted. 2 bits per group ExtendedGrant[2*k+1,2*k], k = 0 to 1 (EXTENDEDGRANT[9:8] is for group number 0, EXTENDEDGRANT[11:10] is for group number 1) 0x1: 1 service for group #k when granted 0x2: 2 services for group #k when granted 0x3: 3 services for group #k when granted 7:2 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00 1:0 HIGHPRIOVECTOR High-priority attribute inside a class RW 0x0 Vector allocating a higher priority to one of the class members. A single group may be given this attribute at a time. HighPrioVector[k], k= 0 to 1 (HIGHPRIOVECTOR[1] is for group number 1, HIGHPRIOVECTOR[0] is for group number 0) 0x0: Group #k has standard priority (LRU based). 0x1: Group #k has the highest priority over all other class members. Table 10-132. Register Call Summary for Register SMS_CLASS_ARBITER1 SDRAM Controller (SDRC) Subsystem • Arbitration Policy: [0] [1] • Arbitration Granularity: [2] • SMS Register Summary: [3] SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated EXTENDEDGRANT HIGHPRIOVECTOR 2289
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This chapter describes the memory s
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Device GPMC External device/ memory
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Public Version www.ti.com General-P
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1 GBytes 512 MBytes 256 MBytes 128
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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nCS nBE0/CLE nWE nADV/ALE CSONTIME=
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nCS nBE0/CLE nWE Public Version www
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Row 0 Row 1 Row 2 Row 3 Row 252 Row
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512 Bytes input Row 0 Row 1 Row 2 R
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M0 Manual mode Rd/Wr/ SW Mode Size0
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M1 M2 M3 M4 Per-sector spares Spare
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M9 Per-sector spares, separate ECC
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GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
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Device GPMC module A [27:17] A [16:
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FCLK CLK nADV nCS nOE A/D bus ClkAc
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FCLK nCS nADV nWE A/D bus AdvWrOffT
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Public Version www.ti.com SDRAM Con
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Device SDRAM controller subsystem R
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MUX1 System address 31 30 29 28 27
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MUX23 System address Address mappin
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Configuration register file Rotatio
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Level 0 Region 0 Public Version www
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OCP slave interface OCP slave port
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BANKALLOCATION = 0b00 BANKALLOCATIO
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Page 143 and 144: Endianism CSnMUXCFG field SDRC.SDRC
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Page 149 and 150: CLK CMD WRITE DQ DQS CLK CMD DQ DQS
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Page 167 and 168: 8 bits 32 bits Y0 U Y1 V P0 P1 16 b
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Page 175 and 176: Request for transaction on class 1
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Page 179 and 180: No A Class 0 empty? Yes Class 1 emp
Page 181 and 182: Status: There are n pending request
Page 183 and 184: 4 GB 0x0000 0000 0x6C00 0000 0x6CFF
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Page 219 and 220: Device D2D OCM_ROM OCM_RAM ROM (32K
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