Chapter 10 Memory Subsystem.pdf

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Public Version SDRAM Controller (SDRC) Subsystem www.ti.com Bits Field Name Description Type Reset 11:9 CS0MUXCFG Identifies the SDRC pins used by CS0 RW See (1) 0x0: 32-bit SDRAM on Datalane[31:0] 0x1: 32-bit SDRAM on Datalane[31:0] 0x2: 16-bit SDRAM on Datalane[31:16] 0x3: 16-bit SDRAM on Datalane[16:0] 0x4: Reserved 0x5: Reserved 0x6: Reserved 0x7: 16-bit SDRAM on Datalane[31:16] 8 SDRCTRISTATE Static 3-state command for the SDRC I/O pads RW See (1) 0x0: All SDRC interface pins are set to hi-Z. 0x1: Normal mode: SDRC drives the I/O pads based on the memory traffic. 7:0 RESERVED Write 0s for future compatibility. Read returns 0s. RW See (1) Table 10-162. Register Call Summary for Register SDRC_SHARING SDRAM Controller (SDRC) Subsystem • CS0-CS1 Memory Spaces: [0] [1] • Data Multiplexing During Write Operations: [2] [3] [4] • Data Demultiplexing During Read Operations: [5] [6] • Memory Configuration: [7] [8] • SDRC Register Summary: [9] Address Offset 0x0000 0048 Table 10-163. SDRC_ERR_ADDR Physical Address 0x6D00 0048 Instance SDRC Description This register captures the address of the last illegal access received on the interconnect. Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ERRORADDRESS Bits Field Name Description Type Reset 31:0 ERRORADDRESS Address of illegal access (Bit 31 is always 0.) R 0x00000000 SDRAM Controller (SDRC) Subsystem • Error Management: [0] • SDRC Register Summary: [1] Table 10-164. Register Call Summary for Register SDRC_ERR_ADDR 2300 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated
Public Version www.ti.com SDRAM Controller (SDRC) Subsystem Address Offset 0x0000 004C Table 10-165. SDRC_ERR_TYPE Physical Address 0x6D00 004C Instance SDRC Description This register provides additional information about the last illegal access. Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED Bits Field Name Description Type Reset 31:12 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x00000 11:8 ERRORCONNID Identifies the interconnect ConnID of the illegal access initiator: Refer to RW 0x0 the top level documentation of the device using the SDRC module. 7 RESERVED Write 0 for future compatibility. Read returns 0. RW 0x0 6:4 ERRORMCMD System command of the transaction that caused the error (3-bit field) RW 0x0 3:2 ERRORADD Flag that indicates access is to an illegal address RW 0x2 Read 0x0: The system request was to an address outside the memory space. Write 0x0: Clear ErrorAdd bit field. Read 0x1: The system request was to an address outside the register space. Write 0x1: No effect Read 0x2: No Err Add. Not an address error Write 0x2: No effect Read 0x3: No Err Add. Not an address error Write 0x3: No effect 1 ERRORDPD Transaction error while the memory is in deep-power-down mode RW 0x0 Read 0x0: The memory was not in deep-power-down mode when the error occurred. Write 0x0: No effect Read 0x1: The error is due to an unexpected access while the memory was in deep-power-down mode. Write 0x1: Clear the ErrorDPD bit field. 0 ERRORVALID Error validity status - Must be explicitly cleared with a write 0 transaction. RW 0x0 Read 0x0: All error fields no longer valid Write 0x0: Clear ErrorValid bit field Read 0x1: Error detected and logged in the other error fields Write 0x1: No effect Table 10-166. Register Call Summary for Register SDRC_ERR_TYPE SDRAM Controller (SDRC) Subsystem • Error Management: [0] [1] [2] [3] [4] • SDRC Register Summary: [5] SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated ERRORCONNID RESERVED ERRORMCMD ERRORADD ERRORDPD ERRORVALID 2301
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This chapter describes the memory s
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Device GPMC External device/ memory
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Public Version www.ti.com General-P
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1 GBytes 512 MBytes 256 MBytes 128
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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nCS nBE0/CLE nWE nADV/ALE CSONTIME=
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nCS nBE0/CLE nWE Public Version www
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Row 0 Row 1 Row 2 Row 3 Row 252 Row
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512 Bytes input Row 0 Row 1 Row 2 R
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M0 Manual mode Rd/Wr/ SW Mode Size0
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M1 M2 M3 M4 Per-sector spares Spare
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M9 Per-sector spares, separate ECC
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GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
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Device GPMC module A [27:17] A [16:
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FCLK CLK nADV nCS nOE A/D bus ClkAc
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FCLK nCS nADV nWE A/D bus AdvWrOffT
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Public Version www.ti.com SDRAM Con
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Device SDRAM controller subsystem R
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MUX1 System address 31 30 29 28 27
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MUX23 System address Address mappin
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Configuration register file Rotatio
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Level 0 Region 0 Public Version www
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OCP slave interface OCP slave port
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BANKALLOCATION = 0b00 BANKALLOCATIO
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Endianism CSnMUXCFG field SDRC.SDRC
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CLK CMD WRITE DQ DQS CLK CMD DQ DQS
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CLK_IN SIGNAL_IN MODEMAXDELAY Initi
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Page 167 and 168: 8 bits 32 bits Y0 U Y1 V P0 P1 16 b
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Chapter 10 Memory Subsystem.pdf

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