Chapter 10 Memory Subsystem.pdf

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CLK_IN DLL i = 0 i = 1 i = 2 i = 3 DQ[7+8 *i; 8*i ] DQS[i] Public Version SDRAM Controller (SDRC) Subsystem www.ti.com Figure 10-59. DLL/CDL Architecture CDL i DDR read CDL 4 DDR write Figure 10-60 shows a simplified block diagram of the DLL/CDL module. D Q Rising edge capture DFF D Q Falling edge capture DFF DLL write CLK, used in DDR mode to launch write data. 2244 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated sdrc-016
CLK_IN SIGNAL_IN MODEMAXDELAY Initial delay Phase detector Control logic C D L Public Version www.ti.com SDRAM Controller (SDRC) Subsystem Figure 10-60. Simplified DLL/CDL Block Diagram C D L C D L C D L DCBFORCE (8 bits) + DLL DLL/CDL C D L SIGNAL_OUT sdrc-017 The DLL circuit contains four delay elements in series. Therefore, the DLL output code and regulator output voltage determine a delay equivalent to one fourth of the reference input period in a stand-alone DLL/CDL (those CDLs are delay elements integrated into the DLL and are not shown in Figure 10-59). In other words, the DLL/CDL delay is equivalent to 90 degrees without DLL/DCDL. 10.2.4.5 Mode Registers 10.2.4.5.1 Mode Register (MR) This register is common to all SDR and DDR SDRAMs. It is a 12-bit register and controls the following parameters: • Write burst mode (SDRC.SDRC_MR_p[9] WBST bit (where p = 0 or 1 for SDRC CS0 or CS1) • CAS latency (SDRC.SDRC_MR_p[6:4] CASL field) • Serial/interleaved mode (SDRC.SDRC_MR_p[3] SIL bit) • Burst length (SDRC.SDRC_MR_p[2:0] BL field) MR is accessible through SDRC.SDRC_MR_p (where p = 0 or 1 for SDRC CS0 or CS1). Writing to SDRC.SDRC_MR_p initiates an implicit load mode register command qualified by BA1, BA0 = 0, 0. 10.2.4.5.2 Extended Mode Register 2 (EMR2) This register is specific to low-power SDR and mobile DDR SDRAM devices. It is a 12-bit register and controls the following parameters: • Temperature-compensated self-refresh (SDRC.SDRC_EMR2_p[4:3] TCSR field) • Partial array self-refresh (SDRC.SDRC_EMR2_p[2:0] PASR field) EMR2 is accessible through SDRC.SDRC_EMR2_p (where p stands for CS0 or CS1). Writing to SDRC.SDRC_EMR2_p initiates an implicit load mode register command qualified by BA1, BA0 = 1, 0. SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated 2245
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This chapter describes the memory s
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Device GPMC External device/ memory
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Public Version www.ti.com General-P
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1 GBytes 512 MBytes 256 MBytes 128
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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nCS nBE0/CLE nWE nADV/ALE CSONTIME=
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nCS nBE0/CLE nWE Public Version www
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Row 0 Row 1 Row 2 Row 3 Row 252 Row
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512 Bytes input Row 0 Row 1 Row 2 R
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M0 Manual mode Rd/Wr/ SW Mode Size0
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M1 M2 M3 M4 Per-sector spares Spare
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M9 Per-sector spares, separate ECC
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GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
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Device GPMC module A [27:17] A [16:
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FCLK CLK nADV nCS nOE A/D bus ClkAc
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FCLK nCS nADV nWE A/D bus AdvWrOffT
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Page 119 and 120: MUX1 System address 31 30 29 28 27
Page 121 and 122: MUX23 System address Address mappin
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Page 135 and 136: OCP slave interface OCP slave port
Page 139 and 140: BANKALLOCATION = 0b00 BANKALLOCATIO
Page 143 and 144: Endianism CSnMUXCFG field SDRC.SDRC
Page 149: CLK CMD WRITE DQ DQS CLK CMD DQ DQS
Page 167 and 168: 8 bits 32 bits Y0 U Y1 V P0 P1 16 b
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Public Version www.ti.com SDRAM Con
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Device D2D OCM_ROM OCM_RAM ROM (32K
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Public Version www.ti.com On-Chip M
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