Chapter 10 Memory Subsystem.pdf

Public Version
General-Purpose Memory Controller www.ti.com
• The RDCYCLETIME and WRCYCLETIME bit fields are programmable in the
GPMC.GPMC_CONFIG5_i register, i = 0 to 7.
• The RDCYCLETIME and WRCYCLETIME bit fields can be set from 0 to 31 GPMC_FCLK cycles with
a granularity of 1 for GPMC.GPMC_CONFIG1_i[4] TIMEPARAGRANULARITY set to 0.
• The RDCYCLETIME and WRCYCLETIME bit fields can be set from 0 to 62 GPMC._FCLK cycles with
a granularity of 2 for GPMC.GPMC_CONFIG1_i[4] TIMEPARAGRANULARITY set to 1.
10.1.5.3.2 nCS: Chip-Select Signal Control Assertion/Deassertion Time
(CSONTIME/CSRDOFFTIME/CSWROFFTIME/CSEXTRADELAY)
The GPMC.GPMC_CONFIG2_i[3:0] CSONTIME field (where i = 0 to 7) defines the nCS signal-assertion
time relative to the start access time. It is common for read and write accesses.
For a read access, the GPMC.GPMC_CONFIG2_i[12:8] CSRDOFFTIME field defines the nCS signal
deassertion time relative to start access time.
For a write access, the GPMC.GPMC_CONFIG2_i[20:16] CSWROFFTIME field defines the nCS signal
deassertion time relative to start access time.\
CSONTIME, CSRDOFFTIME and CSWROFFTIME parameters are applicable to synchronous and
asynchronous modes. CSONTIME can be used to control an address and byte enable setup time before
chip-select assertion. CSRDOFFTIME and CSWROFFTIME can be used to control an address and byte
enable hold time after chip-select deassertion.
nCS signal transitions as controlled through CSONTIME, CSRDOFFTIME, and CSWROFFTIME can be
delayed by half a GPMC_FCLK period by enabling the GPMC.GPMC_CONFIG2_i[7] CSEXTRADELAY
bit. This half of a GPMC_FCLK period provides more granularity on the nCS assertion and deassertion
time to guarantee proper setup and hold time relative to GPMC_CLK. CSEXTRADELAY is especially
useful in configurations where GPMC_CLK and GPMC_FCLK have the same frequency, but can be used
for all GPMC configurations. If asserted, CSEXTRADELAY applies to all parameters controlling nCS
transitions.
The CSEXTRADELAY bit must be used carefully to avoid control-signal overlap between successive
accesses to different chip-selects. This implies the need to program the RDCYCLETIME and
WRCYCLETIME bit fields to be greater than the nCS signal-deassertion time, including the extra
half-GPMC_FCLK-period delay.
10.1.5.3.3 nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time
(ADVONTIME/ADVRDOFFTIME/ADVWROFFTIME/ADVEXTRADELAY)
The GPMC.GPMC_CONFIG3_i[3:0] ADVONTIME field (where i = 0 to 7) defines the nADV/ALE
signal-assertion time relative to start access time. It is common to read and write accesses.
For a read access, the GPMC.GPMC_CONFIG3_i[12:8] ADVRDOFFTIME field defines the nADV/ALE
signal-deassertion time relative to start access time.
For a write access, the GPMC.GPMC_CONFIG3_i[20:16] ADVWROFFTIME field defines the nADV/ALE
signal-deassertion time relative to start access time.
ADVONTIME can be used to control an address and byte enable valid setup time control before
nADV/ALE assertion. ADVRDOFFTIME and ADVWROFFTIME can be used to control an address and
byte enable valid hold time control after nADV/ALE de-assertion. ADVRDOFFTIME and ADVWROFFTIME
are applicable to both synchronous and asynchronous modes.
nADV/ALE signal transitions as controlled through ADVONTIME, ADVRDOFFTIME, and
ADVWROFFTIME can be delayed by half a GPMC_FCLK period by enabling the
GPMC.GPMC_CONFIG3_i[7] ADVEXTRADELAY bit. This half of a GPMC_FCLK period provides more
granularity on nADV/ALE assertion and deassertion time to guarantee proper setup and hold time relative
to GPMC_CLK. The ADVEXTRADELAY configuration parameter is especially useful in configurations
where GPMC_CLK and GPMC_FCLK have the same frequency, but can be used for all GPMC
configurations. If asserted, ADVEXTRADELAY applies to all parameters controlling nADV/ALE transitions.
2112 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011
Copyright © 2010–2011, Texas Instruments Incorporated