Chapter 10 Memory Subsystem.pdf

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www.ti.com General-Purpose Memory Controller
Bits Field Name Description Type Reset
4 WRITEPROTECT Controls the WP output pin level RW 0x0
0x0: WP output pin is low
0x1: WP output pin is high
3:2 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0
1 LIMITEDADDRESS Limited Address device support RW 0x0
0x0: No effect
0x1: A26-A11 are not modified during an external
memory access.
0 NANDFORCEPOSTEDWRITE Enables the Force Posted Write feature to NAND RW 0x0
Cmd/Add/Data location
0x0: Disables Force Posted Write
0x1: Enables Force Posted Write
Table 10-46. Register Call Summary for Register GPMC_CONFIG
General-Purpose Memory Controller
• GPMC Environment: [0]
• GPMC Address and Data Bus: [1] [2]
• WAIT Pin Monitoring Control: [3]
• WRITE PROTECT (nWP): [4]
• Asynchronous Access Description: [5] [6]
• NAND Device Basic Programming Model: [7] [8]
• GPMC Register Summary: [9]
Address Offset 0x0000 0054
Table 10-47. GPMC_STATUS
Physical Address 0x6E00 0054 Instance GPMC
Description The status register provides global status bits of the GPMC
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED
Bits Field Name Description Type Reset
31:12 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00000
11 WAIT3STATUS Is a copy of input pin WAIT3. (Reset value is WAIT3 input R 0xpin
sampled at IC reset)
0x0: WAIT3 asserted (inactive state)
0x1: WAIT3 de-asserted
10 WAIT2STATUS Is a copy of input pin WAIT2. (Reset value is WAIT2 input R 0xpin
sampled at IC reset)
0x0: WAIT2 asserted (inactive state)
0x1: WAIT2 de-asserted
SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem
WAIT3STATUS
WAIT2STATUS
Copyright © 2010–2011, Texas Instruments Incorporated
WAIT1STATUS
WAIT0STATUS
EMPTYWRITEBUFFERSTATUS
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