Chapter 10 Memory Subsystem.pdf
Chapter 10 Memory Subsystem.pdf
Chapter 10 Memory Subsystem.pdf
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Public Version<br />
SDRAM Controller (SDRC) <strong>Subsystem</strong> www.ti.com<br />
<strong>10</strong>.2.4.4.11 Controlled Delay Line<br />
The DLL/CDL module is a hard macro composed of one master delay-locked loop (DLL) and five<br />
slave-controlled delay lines (CDL). It is used to generate precise delays suitable for DDR read and write<br />
operations. DLL delays are tracked at high frequency on process dispersion, and voltage and temperature<br />
variations (PVT) .<br />
A CDL is a component with a clock input signal, a clock output signal, and a delay value input. The output<br />
signal is the input signal delayed according to the delay value.<br />
The DLL output is a command that controls the CDLs (plus the controlled voltage) and assures an output<br />
signal with 90-degree delay with respect to its input signal. The DLL contains five CDL blocks.<br />
<strong>10</strong>.2.4.4.11.1 Purpose of the DLL/CDL Module<br />
In DDR applications, the DLL and CDL combination helps provide a data strobe (DQS) with a delay<br />
suitable to the main read and write RAM operations that exceed 83 MHz. The DLL functions within a<br />
locking range of 83 to 200 Mhz. Below 83 MHz, the DLL must be used in unlocked mode. For lower clock<br />
frequencies, set the DLL to bypass mode.<br />
DLL/CDL is used to delay the incoming DQS in case of DDR read, or delay the output DQ (data lines) in<br />
case of DDR write (and, hence, to increase the ac timing margin). DQS is used only with DDR memory.<br />
There is no need to use the DLL/CDL for the SDR DRAM because data is strobed every clock cycle. The<br />
DQS signals are left unconnected for SDR SDRAM memories.<br />
DQS is propagated with the data (thus reducing the impact of the propagation delay) and is used by the<br />
receiver to sample the data.<br />
The DLL/CDL combination minimizes the negative effects caused by skews and jitters of clock signals.<br />
The delay introduced by the CDL base unit depends on PVT conditions. Moreover, the CDL timing delay<br />
is not a linear function of the DLL counter offset. By means of the DLL feedback loop, the delay value is<br />
updated in real time and is adjusted according to voltage and temperature variations.<br />
DDR interfaces transmit data on both edges of the DQS bidirectional data strobe. Address and control<br />
signals transmit at half the data frequency (that is, at the DDR clock frequency) and latch only on the<br />
rising edge of the transmit clock.<br />
The bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at<br />
the receiver. sdrc_dqs[3:0] is an SDRC I/O that connects the SDRC with DDR SDRAM DQS pins. See<br />
Figure <strong>10</strong>-43 for an overview of DDR SDRAM connection with the SDRC. DQS is transmitted by the DDR<br />
SDRAM during reads and by the SDRC during writes. DQS is edge-aligned with data for reads and<br />
center-aligned with data for writes, as shown in Figure <strong>10</strong>-57.<br />
Figure <strong>10</strong>-57 shows the generic DDR data-write and data-read waveforms.<br />
2242 <strong>Memory</strong> <strong>Subsystem</strong> SPRUGN4L–May 20<strong>10</strong>–Revised June 2011<br />
Copyright © 20<strong>10</strong>–2011, Texas Instruments Incorporated