Chapter 10 Memory Subsystem.pdf

nCS
nBE0/CLE
nWE
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Figure 10-25. NAND Data Write Cycle
CSONTIME=0
WEONTIME=0
WEOFFTIME
DATA[15:0] Data
WRCYCLETIME
CSWROFFTIME = WRCYCLETIME
10.1.5.14.1.6 NAND Device General Chip-Select Timing Control Requirement
For most NAND devices, read data access time is dominated by nCS-to-data-valid timing and has faster
nRE-to-data-valid timing. Successive accesses with nCS deassertions between accesses are affected by
this timing constraint. Because accesses to a NAND device can be interleaved with other chip-select
accesses, there is no certainty that nCS always stays low between two accesses to the same chip-select.
Moreover, an nCS deassertion time between the same chip-select NAND accesses is likely to be required
as follows: the nCS deassertion requires programming CYCLETIME and RDACCESSTIME according to
the nCS-to-data-valid critical timing.
To get full performance from NAND read and write accesses, the prefetch engine can dynamically reduce
RDCYCLETIME, WRCYCLETIME, RDACCESSTIME, WRACCESSTIME, CSRDOFFTIME,
CSWROFFTIME, ADVRDOFFTIME, ADVWROFFTIME, OEOFFTIME, and WEOFFTIME on back-to-back
NAND accesses (to the same memory) and suppress the minimum nCS high pulse width between
accesses. For more information about optimal prefetch engine access, see Section 10.1.5.14.4, Prefetch
and Write-Posting Engine.
Some NAND devices require minimum write-to-read idle time, especially for device-status read accesses
following status-read command programming (write access). If such write-to-read transactions are used, a
minimum nCS high pulse width must be set. For this, CYCLE2CYCLESAMECSEN and
CYCLE2CYCLEDELAY must be set according to the appropriate timing requirement to prevent any timing
violation.
NAND devices usually have an important nRE high to data bus in tristate mode. This requires a bus
turnaround setting (BUSTURNAROUND = 1) so that the next access to a different chip-select is delayed
until the BUSTURNAROUND delay completes. Back-to-back NAND read accesses to the same NAND
flash are not affected by the programmed bus turnaround delay.
10.1.5.14.1.7 Read and Write Access Size Adaptation
10.1.5.14.1.7.1 8-Bit Wide NAND Device
Host Word16 and Word32 read and write access requests to a chip-select associated with an 8-bit wide
NAND device are split into successive read and write byte accesses to the NAND memory device. Byte
access is ordered according to little-endian organization. A NAND 8-bit-wide device must be interfaced on
the D0D7 interface bus lane. GPMC data accesses are justified on this bus lane when the chip-select is
associated with an 8-bit wide NAND device.
10.1.5.14.1.7.2 16-Bit Wide NAND Device
Host Word32 read and write access requests to a chip-select associated with a 16-bit wide NAND device
are split into successive read and write Word16 accesses to the NAND memory device. Word16 access is
ordered according to little-endian organization.
SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem
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