Chapter 10 Memory Subsystem.pdf

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Table 10-3. Idle Cycle Insertion Configuration (continued)
1st BUSTURN Second Chip- Add/Data CYCLE2 CYCLE2 Idle Cycle Insertion
Access AROUND Access Select Multiplexed CYCLE CYCLE Between the Two
Type Timing Type SAMECSEN DIFFCSEN Accesses
Parameter Parameter Parameter
R/W > 0 R/W Same Any 1 x CYCLE2CYCLEDELAY cycles
are inserted. If BTA idle cycles
already apply on these two
back-to-back accesses, the
effective delay is max
(BUSTURNAROUND,
CYCLE2CYCLEDELAY).
R/W > 0 R/W Different Any x 1 CYCLE2CYCLEDELAY cycles
are inserted. If BTA idle cycles
already apply on these two
back-to-back accesses, the
effective delay is maximum
(BUSTURNAROUND,
CYCLE2CYCLEDELAY).
10.1.5.4.7 Slow Device Support (TIMEPARAGRANULARITY Parameter)
All access-timing parameters can be multiplied by 2 by setting the GPMC.GPMC_CONFIG1_i[4]
TIMEPARAGRANULARITY bit (where i stands for the GPMC chip-select value, i = 0 to 7). Increasing all
access timing parameters allows support of slow devices.
10.1.5.5 gpmc_io_dir Pin
The gpmc_io_dir pin is used to control I/O direction on the GPMC data bus gpmc_d[15:0]. Depending on
top-level pad multiplexing, this signal can be output and used externally to the device, if required.
The gpmc_io_dir pin is low during transmit (OUT) and high during receive (IN).
For write accesses, the gpmc_io_dir pin stays OUT from start-cycle time to end-cycle time.
For read accesses, the gpmc_io_dir pin goes from OUT to IN at nOE assertion time and stays IN until:
• BUSTURNAROUND is enabled:
– The gpmc_io_dir pin goes from IN to OUT at end-cycle time plus programmable bus turnaround
time.
• BUSTURNAROUND is disabled:
– After an asynchronous read access, the gpmc_io_dir pin goes from IN to OUT at RDACCESSTIME
+ 1 GPMC_FCLK cycle or when RDCYCLETIME completes, whichever occurs last.
– After a synchronous read access, the gpmc_io_dir pin goes from IN to OUT at RDACCESSTIME +
2 GPMC_FCLK cycles or when RDCYCLETIME completes, whichever occurs last.
Because of the bus-keeping feature of the GPMC, after a read or write access and with no other accesses
pending, the default value of the gpmc_io_dir pin is OUT (see Section 10.1.5.3.10, Bus Keeping Support).
To prevent unnecessary toggling, the gpmc_io_dir pin stays IN between two successive read accesses to
a nonmultiplexed device (address mapping supports nonmultiplexed 16-bit wide devices with limited
address (2 Kbytes)).
Figure 10-10 shows address mapping in nonmultiplexed mode with a limited address range (A[10:1]).
10.1.5.6 Reset
No reset signal is sent to the external memory device by the GPMC. For more information see Chapter 3,
Power, Reset, and Clock Management.
The PRCM module provides an input pin, global_rst_n, to the GPMC:
• The global_rst_n pin is activated during device warm reset and cold reset.
• The global_rst_n pin initializes the internal state-machine and the internal configuration registers.
2122 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011
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