Chapter 10 Memory Subsystem.pdf

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Public Version General-Purpose Memory Controller www.ti.com Address Offset 0x0000 0018 Table 10-35. GPMC_IRQSTATUS Physical Address 0x6E00 0018 Instance GPMC Description This interrupt status register regroups all the status of the module internal events that can generate an interrupt. Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED Bits Field Name Description Type Reset 31:12 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00000 11 WAIT3EDGEDETECTION Status of the Wait3 Edge Detection interrupt RW 0x0 STATUS Read 0x0: A transition on WAIT3 input pin has not been detected WAIT3EDGEDETECTIONSTATUS WAIT2EDGEDETECTIONSTATUS WAIT1EDGEDETECTIONSTATUS WAIT0EDGEDETECTIONSTATUS Write 0x0: WAIT3EDGEDETECTIONSTATUS bit unchanged Read 0x1: A transition on WAIT3 input pin has been detected Write 0x1: WAIT3EDGEDETECTIONSTATUS bit is reset 10 WAIT2EDGEDETECTION Status of the Wait2 Edge Detection interrupt RW 0x0 STATUS Read 0x0: A transition on WAIT2 input pin has not been detected Write 0x0: WAIT2EDGEDETECTIONSTATUS bit unchanged Read 0x1: A transition on WAIT2 input pin has been detected Write 0x1: WAIT2EDGEDETECTIONSTATUS bit is reset 9 WAIT1EDGEDETECTION Status of the Wait1 Edge Detection interrupt RW 0x0 STATUS Read 0x0: A transition on WAIT1 input pin has not been detected Write 0x0: WAIT1EDGEDETECTIONSTATUS bit unchanged Read 0x1: A transition on WAIT1 input pin has been detected Write 0x1: WAIT1EDGEDETECTIONSTATUS bit is reset 8 WAIT0EDGEDETECTION Status of the Wait0 Edge Detection interrupt RW 0x0 STATUS Read 0x0: A transition on WAIT0 input pin has not been detected Write 0x0: WAIT0EDGEDETECTIONSTATUS bit unchanged Read 0x1: A transition on WAIT0 input pin has been detected Write 0x1: WAIT0EDGEDETECTIONSTATUS bit is reset 7:2 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00 1 TERMINALCOUNTSTATUS Status of the TerminalCountEvent interrupt RW 0x0 Read 0x0: Indicates that CountValue is greater than 0 Write 0x0: TERMINALCOUNTSTATUS bit unchanged Read 0x1: Indicates that CountValue is equal to 0 Write 0x1: TERMINALCOUNTSTATUS bit is reset 2180 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated TERMINALCOUNTSTATUS FIFOEVENTSTATUS
Public Version www.ti.com General-Purpose Memory Controller Bits Field Name Description Type Reset 0 FIFOEVENTSTATUS Status of the FIFOEvent interrupt RW 0x0 Read 0x0: Indicates than less than FIFOThreshold bytes are available in prefetch mode and less than FIFOThreshold bytes free places are available in write-posting mode. Write 0x0: FIFOEVENTSTATUS bit unchanged Read 0x1: Indicates than at least FIFOThreshold bytes are available in prefetch mode and at least FIFOThreshold bytes free places are available in write-posting mode. Write 0x1: FIFOEVENTSTATUS bit is reset Table 10-36. Register Call Summary for Register GPMC_IRQSTATUS General-Purpose Memory Controller • NAND Device Basic Programming Model: [0] [1] [2] [3] [4] [5] [6] • GPMC Register Summary: [7] Address Offset 0x0000 001C Table 10-37. GPMC_IRQENABLE Physical Address 0x6E00 001C Instance GPMC Description The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis. Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED Bits Field Name Description Type Reset 31:12 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00000 11 WAIT3EDGEDETECTION Enables the Wait3 Edge Detection interrupt RW 0x0 ENABLE 0x0: Wait3EdgeDetection interrupt is masked 0x1: Wait3EdgeDetection event generates an interrupt if occurs 10 WAIT2EDGEDETECTION Enables the Wait2 Edge Detection interrupt RW 0x0 ENABLE 0x0: Wait2EdgeDetection interrupt is masked 0x1: Wait2EdgeDetection event generates an interrupt if occurs 9 WAIT1EDGEDETECTION Enables the Wait1 Edge Detection interrupt RW 0x0 ENABLE 0x0: Wait1EdgeDetection interrupt is masked 0x1: Wait1EdgeDetection event generates an interrupt if occurs 8 WAIT0EDGEDETECTION Enables the Wait0 Edge Detection interrupt RW 0x0 ENABLE 0x0: Wait0EdgeDetection interrupt is masked 0x1: Wait0EdgeDetection event generates an interrupt if occurs 7:2 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00 SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem WAIT3EDGEDETECTIONENABLE WAIT2EDGEDETECTIONENABLE Copyright © 2010–2011, Texas Instruments Incorporated WAIT1EDGEDETECTIONENABLE WAIT0EDGEDETECTIONENABLE TERMINALCOUNTEVENTENABLE FIFOEVENTENABLE 2181
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This chapter describes the memory s
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Device GPMC External device/ memory
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Public Version www.ti.com General-P
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1 GBytes 512 MBytes 256 MBytes 128
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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Page 37 and 38: GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
Page 43 and 44: GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
Page 47 and 48: nCS nBE0/CLE nWE nADV/ALE CSONTIME=
Page 49 and 50: nCS nBE0/CLE nWE Public Version www
Page 53 and 54: Row 0 Row 1 Row 2 Row 3 Row 252 Row
Page 55 and 56: 512 Bytes input Row 0 Row 1 Row 2 R
Page 61 and 62: M0 Manual mode Rd/Wr/ SW Mode Size0
Page 65 and 66: M1 M2 M3 M4 Per-sector spares Spare
Page 67 and 68: M9 Per-sector spares, separate ECC
Page 73 and 74: GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
Page 75 and 76: Device GPMC module A [27:17] A [16:
Page 77 and 78: FCLK CLK nADV nCS nOE A/D bus ClkAc
Page 79 and 80: FCLK nCS nADV nWE A/D bus AdvWrOffT
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Page 111 and 112: Public Version www.ti.com SDRAM Con
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Page 119 and 120: MUX1 System address 31 30 29 28 27
Page 121 and 122: MUX23 System address Address mappin
Page 125 and 126: Configuration register file Rotatio
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Page 135 and 136: OCP slave interface OCP slave port
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Public Version www.ti.com SDRAM Con
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BANKALLOCATION = 0b00 BANKALLOCATIO
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Endianism CSnMUXCFG field SDRC.SDRC
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CLK CMD WRITE DQ DQS CLK CMD DQ DQS
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CLK_IN SIGNAL_IN MODEMAXDELAY Initi
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8 bits 32 bits Y0 U Y1 V P0 P1 16 b
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Start configuration of VRFB context
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Initiator: Camera subsystem SDRC Su
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Request for transaction on class 1
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Class 1 and class 2 request for tra
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No A Class 0 empty? Yes Class 1 emp
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Status: There are n pending request
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4 GB 0x0000 0000 0x6C00 0000 0x6CFF
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Device D2D OCM_ROM OCM_RAM ROM (32K
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Public Version www.ti.com On-Chip M
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