Chapter 10 Memory Subsystem.pdf

GPMC_FCLK
nCS
nBE0/CLE
nOE/nRE
nADV/ALE
DATA[15:0]
WAIT
RDACCESSTIME
First read access
RDCYCLETIME
CSRDOFFTIME
CSONTIME = 0
OEONTIME = 0
OEOFFTIME
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accesses to other chip-selects (that is, interleaved accesses) occur. Similarly, the access engine also
eliminates the CYCLE2CYCLEDELAY even if CYCLE2CYCLESAMECSEN is set. This capability is limited
to the prefetch and write-posting engine accesses, and MPU accesses to a NAND memory device
(through the defined chip-select memory region or through the GPMC.GPMC_NAND_DATA_i location, i =
0 to 7) are never optimized.
The GPMC.GPMC_PREFETCH_CONFIG1[27] ENABLEOPTIMIZEDACCESS bit must be set to enable
optimized accesses. To optimize access time, the GPMC.GPMC_PREFETCH_CONFIG1[30:28]
CYCLEOPTIMIZATION field defines the number of GPMC_FCLK cycles to be suppressed from the
RDCYCLETIME, WRCYCLETIME, RDACCESSTIME, WRACCESSTIME, CSOFFTIME, ADVOFFTIME,
OEOFFTIME, and WEOFFTIME timing parameters.
Figure 10-36 highlights that, in the case of back-to-back accesses to the NAND flash through the prefetch
engine, CYCLE2CYCLESAMECSEN is forced to 0 when using optimized accesses. The first access uses
the regular timing settings for this chip-select. All accesses after this one use settings reduced by x clock
cycles, x being defined by the GPMC_PREFETCH_CONFIG1[30:28] CYCLEOPTIMIZATION field.
Figure 10-36. NAND Read Cycle Optimization Timing Description
RDACCESSTIME - x clk cycles
Second read access
RDCYCLETIME − x clk cycles
CSRDOFFTIME − x clk cycles
CSONTIME = 0
OEONTIME = 0
OEOFFTIME − x clk cycles
Data 0 Data 1
x is the programmed value in the
GPMC_PREFETCH_CONFIG1[30:28]
CYCLEOPTIMIZATION field
10.1.5.14.4.7 Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
Any on-going read or write access from the prefetch and write-posting engine is completed before an
access to any other chip-select can be initiated. As a default, the arbiter uses a fixed-priority algorithm,
and the prefetch and write-posting engine has the lowest priority. The maximum latency added to access
starting time in this case equals the RDCYCLETIME or WRCYCLETIME (optimized or not) plus the
requested BUSTURNAROUND delay for bus turnaround completion programmed for the chip-select to
which the NAND device is connected to.
Alternatively, a round-robin arbitration can be used to prioritize accesses to the external bus. This
arbitration scheme is enabled by setting the GPMC.GPMC_PREFETCH_CONFIG1[23]
SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem
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