Chapter 10 Memory Subsystem.pdf

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Public Version General-Purpose Memory Controller www.ti.com PFPWENROUNDROBIN bit. When a request to another chip-select is received while the prefetch and write-posting engine is active, priority is given to the new request. The request processed thereafter is the prefetch and write-posting engine request, even if another interconnect request is passed in the mean time. The engine keeps control of the bus for an additional number of requests programmed in the GPMC.GPMC_PREFETCH_CONFIG1[19:16] PFPWWEIGHTEDPRIO bit field. Control is then passed to the direct interconnect request. As an example, the round-robin arbitration scheme is selected with PFPWWEIGHTEDPRIO set to 0x2. Considering the prefetch and write-posting engine and the interconnect interface are always requesting access to the external interface, the GPMC grants priority to the direct interconnect access for one request. The GPMC then grants priority to the engine for three requests, and finnaly back to the direct interconnect access, until the arbiter is reset when one of the two initiators stops initiating requests. 10.1.6 GPMC Use Cases and Tips 10.1.6.1 How to Set GPMC Timing Parameters for Typical Accesses 10.1.6.1.1 External Memory Attached to the GPMC Module As discussed in the introduction to this chapter, the GPMC module supports the following external memory types: • Asynchronous or synchronous, 8-bit or 16-bit-width memory or device • 16-bit address/data-multiplexed or not multiplexed NOR flash device • 8- or 16-bit NAND flash device The following examples show how to calculate GPMC timing parameters by showing a typical parameter setup for the access to be performed. The example is based on a 512-Mb multiplexed NOR flash memory with the following characteristics: • Type: NOR flash (address/data-multiplexed mode) • Size: 512M bits • Data Bus: 16 bits wide • Speed: 104-MHz clock frequency • Read access time: 80 ns 10.1.6.1.2 Typical GPMC Setup Table 10-17 lists some of the I/Os of the GPMC module. Signal Name I/O Description Table 10-17. GPMC Signals GPMC_FCLK Internal Functional and interface clock. Acts as the time reference. gpmc_clk I/O External clock provided to the external device for synchronous operations gpmc_a[11: 1] O Address gpmc_d[15: 0] I/O Data-multiplexed with addresses A[16:1] on memory side gpmc_ncs O Chip-select gpmc_nadv_ale O Address valid enable gpmc_noe_nre O Output enable (read access only) gpmc_nwe O Write enable (write access only) gpmc_wait[3:0] I Ready signal from memory device. Indicates when valid burst data is ready to be read 2168 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated
Device GPMC module A [27:17] A [16:1] / D [15:0] CS0 ADV /ALE OE / RE WE WP WAIT0 DEVICECLK Public Version www.ti.com General-Purpose Memory Controller Figure 10-37 shows the typical connection between the GPMC module and an attached NOR flash memory. Figure 10-37. GPMC Connection to an External NOR Flash Memory gpmc_a[11:1] gpmc_d[15:0] gpmc_ncs0 gpmc_nadv_ale gpmc_noe_nre gpmc_nwe gpmc_nwp gpmc_wait0 gpmc_clk A [26:16] A/DQ [15:0] nCE nAVD nOE nWE nWP RDY CLK NOR Flash gpmc_037 The following sections demonstrate how to calculate GPMC parameters for three access types: • Synchronous burst read • Asynchronous read • Asynchronous single write 10.1.6.1.2.1 GPMC Configuration for Synchronous Burst Read Access The clock runs at 104 MHz ( f = 104 MHz; T = 9, 615 ns). Table 10-18 shows the timing parameters (on the memory side) that determine the parameters on the GPMC side. Table 10-19 shows how to calculate timings for the GPMC using the memory parameters. Figure 10-38 shows the synchronous burst read access. Table 10-18. Useful Timing Parameters on the Memory Side AC Read Characteristics on the Description Duration (ns) Memory Side tCES nCS setup time to clock 0 tACS Address setup time to clock 3 tIACC Synchronous access time 80 SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem2169 Copyright © 2010–2011, Texas Instruments Incorporated
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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OCP slave interface OCP slave port
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Endianism CSnMUXCFG field SDRC.SDRC
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CLK CMD WRITE DQ DQS CLK CMD DQ DQS
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4 GB 0x0000 0000 0x6C00 0000 0x6CFF
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Device D2D OCM_ROM OCM_RAM ROM (32K
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