Chapter 10 Memory Subsystem.pdf

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Row 0 Row 1 Row 2 Row 3 Row 252 Row 253 Row 254 Row 255 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P1o P1o P1o P1o P2o P2o 256 Bytes input Row 0 Row 1 Row 2 Row 3 Row 252 Row 253 Row 254 Row 255 Public Version General-Purpose Memory Controller www.ti.com Figure 10-27. Hamming Code Accumulation Algorithm (2/2) P8e P8e P8e P8e Row 0 Row 1 Row 2 Row 3 Row 252 Row 253 Row 254 Row 255 Unused parity bits in the result registers are set to 0. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P1o bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P1o P1e P1o P1e P1o P1e P1o P1e P2o P2e P2o P2e P4o P4e P1o P1o P1o P2o P2o P8e P8o P8e P8o P8e P8o P8e P8o P16e P16o P16e P16o P8e P8e P8e P8e P16e P16e gpmc-027 Figure 10-28 shows ECC computation for a 256-byte data stream (read or write). The result includes six column parity bits (P1o-P2o-P4o for odd parities, and P1e-P2e-P4e for even parities) and sixteen row parity bits (P8o-P16o-P32o--P1024o for odd parities, and P8e-P16e-P32e--P1024e for even parities). Figure 10-28. ECC Computation for a 256-Byte Data Stream (Read or Write) P1024e P1024o gpmc-028 Figure 10-29 shows ECC computation for a 512-byte data stream (read or write). The result includes six column parity bits (P1o-P2o-P4o for odd parities, and P1e-P2e-P4e for even parities) and eighteen row parity bits (P8o-P16o-P32o--P1024o- - P2048o for odd parities, and P8e-P16e-P32e--P1024e- P2048e for even parities). 2148 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated
512 Bytes input Row 0 Row 1 Row 2 Row 3 Row 508 Row 509 Row 510 Row 511 Public Version www.ti.com General-Purpose Memory Controller Figure 10-29. ECC Computation for a 512-Byte Data Stream (Read or Write) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P1o P1e P1o P1e P1o P1e P1o P1e P2o P2e P2o P2e P4o P4e P8e P8o P8e P8o P8e P8o P8e P8o P16e P16o P16e P16o P2048e P2048o gpmc-029 For a 2-Kbytes page, four 512-byte ECC calculations plus one for the spare area are required. Results are stored in the GPMC_ECCj_RESULT registers (j = 1 to 9). 10.1.5.14.3.1.4 ECC Comparison and Correction To detect an error, the computed ECC result must be XORed with the parity value stored in the spare area of the accessed page. • If the result of this logical XOR is all 0s, no error is detected and the read data is correct. • If every second bit in the parity result is a 1, one bit is corrupted and is located at bit address (P2048o, P1024o, P512o, P256o, P128o, P64o, P32o, P16o, P8o, P4o, P2o, P1o). The software must correct the corresponding bit. • If only one bit in the parity result is 1, it is an ECC error and the read data is correct. 10.1.5.14.3.1.5 ECC Calculation Based on 8-Bit Word The 8-bit based ECC computation is used for 8-bit wide NAND device interfacing. The 8-bit based ECC computation can be used for 16-bit wide NAND device interfacing to get backward compatibility on the error-handling strategy used with 8-bit wide NAND devices. In this case, the 16-bit wide data read from or written to the NAND device is fragmented into 2 bytes. According to little-endian access, the least significant bit (LSB) of the 16-bit wide data is ordered first in the byte stream used for 8-bit based ECC computation. 10.1.5.14.3.1.6 ECC Calculation Based on 16-Bit Word ECC computation based on a 16-bit word is used for 16-bit wide NAND device interfacing. This ECC computation is not supported when interfacing an 8-bit wide NAND device, and the GPMC.GPMC_ECC_CONFIG[7] ECC16B bit must be set to 0 when interfacing an 8-bit wide NAND device. The parity computation based on 16-bit words affects the row and column parity mapping. The main difference is that the odd and even parity bits P8o and P8e are computed on rows for an 8-bit based ECC while there are computed on columns for a 16-bit based ECC. Figure 10-30 and Figure 10-31 show a 128 Word 16 ECC computation scheme and a 256 Word16 ECC computation scheme. SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated 2149
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This chapter describes the memory s
Page 3 and 4: Device GPMC External device/ memory
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Page 13 and 14: 1 GBytes 512 MBytes 256 MBytes 128
Page 17 and 18: GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
Page 25 and 26: GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
Page 43 and 44: GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
Page 47 and 48: nCS nBE0/CLE nWE nADV/ALE CSONTIME=
Page 49 and 50: nCS nBE0/CLE nWE Public Version www
Page 53: Row 0 Row 1 Row 2 Row 3 Row 252 Row
Page 61 and 62: M0 Manual mode Rd/Wr/ SW Mode Size0
Page 65 and 66: M1 M2 M3 M4 Per-sector spares Spare
Page 67 and 68: M9 Per-sector spares, separate ECC
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Public Version www.ti.com General-P
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Public Version www.ti.com SDRAM Con
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Device SDRAM controller subsystem R
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MUX1 System address 31 30 29 28 27
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MUX23 System address Address mappin
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Configuration register file Rotatio
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Level 0 Region 0 Public Version www
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OCP slave interface OCP slave port
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BANKALLOCATION = 0b00 BANKALLOCATIO
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Endianism CSnMUXCFG field SDRC.SDRC
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CLK CMD WRITE DQ DQS CLK CMD DQ DQS
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CLK_IN SIGNAL_IN MODEMAXDELAY Initi
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8 bits 32 bits Y0 U Y1 V P0 P1 16 b
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Start configuration of VRFB context
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Initiator: Camera subsystem SDRC Su
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Request for transaction on class 1
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Class 1 and class 2 request for tra
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No A Class 0 empty? Yes Class 1 emp
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Status: There are n pending request
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4 GB 0x0000 0000 0x6C00 0000 0x6CFF
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Device D2D OCM_ROM OCM_RAM ROM (32K
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Public Version www.ti.com On-Chip M
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