Chapter 10 Memory Subsystem.pdf

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1 Gbyte SDRC address space 8 partitions 0x4000 0000 0x3000 0000 0x2000 0000 0x0200 0000 0x0000 0000 128M-byte address space 32M-byte address space 32M-byte address space 32M-byte address space 32M-byte address space Public Version SDRAM Controller (SDRC) Subsystem www.ti.com Therefore, for a start address of 0x2000 0000 (SDRC point of view) when connecting a 2048-Mbit SDRAM memory (64M * 32 such as in MUX25, Table 10-97), the SDRC_CS_CFG[9:8] CS1STARTLOW bit field must be set to 0x00 (the first 32M-byte address space, as shown in Figure 10-77), and the SDRC_CS_CFG[3:0] CS1STARTHIGH bit field must be set to 0x0100 (fourth 128M-byte address space). The start address must be aligned on the memory size. The CS1 end address (0x3000 0000) can be deduced from the CS1 size ( that is, from the RAMSIZE parameter), which takes the value 0x80 when connecting a 2048-Mbit SDRAM memory. Figure 10-77. CS Start and End Address Configuration Example 10.2.6.4 How to Choose a Suitable SDRAM CS1 SDRAM 2048Mb / 256MB address space CS0 SDRAM 256Mb / 32 MB address space Illegal address space - Accessing this address range generates an error CS1 max address, defined by SDRC_MCFG_1[17:8] RAMSIZE = 0x80 CS1 start address slot defined by SDRC_CS_CFG[9:8] CS1STARTLOW = 0x00 and SDRC_CS_CFG[3:0] CS1STARTHIGH = 0x0100 Illegal address space - Accessing this address range generates an error CS0 max address, defined by SDRC_MCFG_0[17:8] RAMSIZE = 0x010 CS0 start address slot fixed interconnect address 0x0000 0000 This section describes how to select a suitable SDRAM device to interface with the SDRC. Basically, if an SDRAM device is aligned with the JEDEC LPDDR1 SDRAM standard (JEDEC committee JC42.3), the SDRAM device is likely to be compatible with the SDRC. To ensure that an SDRAM device is fully compatible, see the following sections. Section 10.2.6.4.1 discusses the SDRAM device features to consider. Section 10.2.6.4.2 discusses the SDRC features to consider. As an example, Section 10.2.6.4.3 lists chosen SDRAM parameters versus the supported characteristics of the SDRC. 10.2.6.4.1 SDRAM Device Parameters Several settings must be considered when selecting an SDRAM device to interface with the SDRC: 2280 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated sdrc-041
Public Version www.ti.com SDRAM Controller (SDRC) Subsystem • SDRAM type • Operating voltage • Maximum operating frequency • Maximum memory size • Memory organization: – Number of banks – Data bus width • Burst length • Page size • Column address strobe (CAS) latency • Refresh rate • AC timing parameters and especially the access time parameter tAC These parameters are defined in the SDRAM device datasheet and must meet the SDRC specifications. 10.2.6.4.2 SDRC Characteristics Keeping the SDRAM device settings in mind, the SDRC supports: • Supported device type: Up to two mobile single data rate (M-SDR) SDRAMs, or up to two low-power double data rate (LPDDR) SDRAMs. • Maximum supported memory size: 128MB per external SDRAM bank (256- and 512-MB SDRAM may be supported, depending on their implementation) • Minimum supported memory size: 2MB • Maximum SDRC addressing capability: 1GB • Memory organization: – Number of internal SDRAM banks: two (for 2-MB and 4-MB memory device only) or four banks (other memory device only) – Data path to external SDRAM memory: 16- or 32-bit • Burst Length: Burst of 2 (M-SDR) and burst of 4 (LPDDR) • Page size: Programmable value (up to 16K bytes) • Column address strobe latency (CL): 1 to 5 system clock cycles • Refresh intervals: Programmable value • Major operation is 3-3-3 (CL-tRCD-tRP) conditions. – CL = 3 – tRCD = 3 clocks cycle time – tRP = 3 clocks cycle time – tRRD = 2 clocks cycle time – tRAS = 7 clocks cycle time – tRC = 10 clocks cycle time 10.2.6.4.3 SDRAM Device Compatibility Verification In this example, a mobile DDR SDRAM memory with the following characteristics is verified for compatibilty: • Type: Mobile DDR SDRAM • Size: 512 Mbits (16M * 32 in 4 banks) Table 10-110 lists the SDRAM versus the SDRC characteristics. SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated 2281
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This chapter describes the memory s
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Device GPMC External device/ memory
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Public Version www.ti.com General-P
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1 GBytes 512 MBytes 256 MBytes 128
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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nCS nBE0/CLE nWE nADV/ALE CSONTIME=
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Row 0 Row 1 Row 2 Row 3 Row 252 Row
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512 Bytes input Row 0 Row 1 Row 2 R
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M0 Manual mode Rd/Wr/ SW Mode Size0
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M1 M2 M3 M4 Per-sector spares Spare
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M9 Per-sector spares, separate ECC
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GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
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Device SDRAM controller subsystem R
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MUX1 System address 31 30 29 28 27
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MUX23 System address Address mappin
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